/****************************************************************************
*
* Invalidate the Data cache for the given address range.
* If the bytes specified by the address (adr) are cached by the Data cache,
* the cacheline containing that byte is invalidated. If the cacheline
* is modified (dirty), the modified contents are lost and are NOT
* written to system memory before the line is invalidated.
*
* @param Start address of range to be invalidated.
* @param Length of range to be invalidated in bytes.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void Xil_DCacheInvalidateRange(unsigned int adr, unsigned len)
{
const unsigned cacheline = 32;
unsigned int end;
unsigned int tempadr = adr;
unsigned int tempend;
unsigned int currmask;
volatile u32 *L2CCOffset = (volatile u32 *) (XPS_L2CC_BASEADDR +
XPS_L2CC_CACHE_INVLD_PA_OFFSET);
currmask = mfcpsr();
mtcpsr(currmask | IRQ_FIQ_MASK);
if (len != 0) {
end = tempadr + len;
tempend = end;
/* Select L1 Data cache in CSSR */
mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
if (tempadr & (cacheline-1)) {
tempadr &= ~(cacheline - 1);
Xil_L1DCacheFlushLine(tempadr);
/* Disable Write-back and line fills */
Xil_L2WriteDebugCtrl(0x3);
Xil_L2CacheFlushLine(tempadr);
/* Enable Write-back and line fills */
Xil_L2WriteDebugCtrl(0x0);
Xil_L2CacheSync();
tempadr += cacheline;
}
if (tempend & (cacheline-1)) {
tempend &= ~(cacheline - 1);
Xil_L1DCacheFlushLine(tempend);
/* Disable Write-back and line fills */
Xil_L2WriteDebugCtrl(0x3);
Xil_L2CacheFlushLine(tempend);
/* Enable Write-back and line fills */
Xil_L2WriteDebugCtrl(0x0);
Xil_L2CacheSync();
}
while (tempadr < tempend) {
/* Invalidate L2 cache line */
*L2CCOffset = tempadr;
dsb();
#ifdef __GNUC__
/* Invalidate L1 Data cache line */
__asm__ __volatile__("mcr " \
XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (tempadr));
#else
{ volatile register unsigned int Reg
__asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
Reg = tempadr; }
#endif
tempadr += cacheline;
}
}
unsigned int sys_irq_save_disable(void)
{
unsigned int state = mfcpsr() & XIL_EXCEPTION_ALL;
if (XIL_EXCEPTION_ALL != state) {
Xil_ExceptionDisableMask(XIL_EXCEPTION_ALL);
}
return state;
}
/****************************************************************************
*
* Invalidate a Data cache line. If the byte specified by the address (adr)
* is cached by the Data cache, the cacheline containing that byte is
* invalidated. If the cacheline is modified (dirty), the modified contents
* are lost and are NOT written to system memory before the line is
* invalidated.
*
* @param Address to be flushed.
*
* @return None.
*
* @note The bottom 4 bits are set to 0, forced by architecture.
*
****************************************************************************/
void Xil_DCacheInvalidateLine(unsigned int adr)
{
unsigned int currmask;
currmask = mfcpsr();
mtcpsr(currmask | IRQ_FIQ_MASK);
Xil_L2CacheInvalidateLine(adr);
Xil_L1DCacheInvalidateLine(adr);
mtcpsr(currmask);
}
/****************************************************************************
*
* Invalidate a Data cache line. If the byte specified by the address (adr)
* is cached by the Data cache, the cacheline containing that byte is
* invalidated. If the cacheline is modified (dirty), the modified contents
* are lost and are NOT written to system memory before the line is
* invalidated.
*
* @param Address to be flushed.
*
* @return None.
*
* @note The bottom 4 bits are set to 0, forced by architecture.
*
****************************************************************************/
void Xil_DCacheInvalidateLine(u32 adr)
{
u32 currmask;
currmask = mfcpsr();
mtcpsr(currmask | IRQ_FIQ_MASK);
Xil_L2CacheInvalidateLine(adr);
Xil_L1DCacheInvalidateLine(adr);
mtcpsr(currmask);
}
/****************************************************************************
*
* Invalidate the entire Data cache.
*
* @param None.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void Xil_DCacheInvalidate(void)
{
u32 currmask;
currmask = mfcpsr();
mtcpsr(currmask | IRQ_FIQ_MASK);
Xil_L2CacheInvalidate();
Xil_L1DCacheInvalidate();
mtcpsr(currmask);
}
/****************************************************************************
*
* Invalidate a Data cache line. If the byte specified by the address (adr)
* is cached by the Data cache, the cacheline containing that byte is
* invalidated. If the cacheline is modified (dirty), the modified contents
* are lost and are NOT written to system memory before the line is
* invalidated.
*
* @param Address to be flushed.
*
* @return None.
*
* @note The bottom 4 bits are set to 0, forced by architecture.
*
****************************************************************************/
void Xil_DCacheInvalidateLine(u32 adr)
{
u32 currmask;
currmask = mfcpsr();
mtcpsr(currmask | IRQ_FIQ_MASK);
#ifndef USE_AMP
Xil_L2CacheInvalidateLine(adr);
#endif
Xil_L1DCacheInvalidateLine(adr);
mtcpsr(currmask);
}
/****************************************************************************
*
* Invalidate a Data cache line. If the byte specified by the address (adr)
* is cached by the Data cache, the cacheline containing that byte is
* invalidated. If the cacheline is modified (dirty), the modified contents
* are lost and are NOT written to system memory before the line is
* invalidated.
*
* @param Address to be flushed.
*
* @return None.
*
* @note The bottom 4 bits are set to 0, forced by architecture.
*
****************************************************************************/
void Xil_DCacheInvalidateLine(INTPTR adr)
{
u32 currmask;
currmask = mfcpsr();
mtcpsr(currmask | IRQ_FIQ_MASK);
mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F)));
/* Wait for invalidate to complete */
dsb();
mtcpsr(currmask);
}
/*
* This optional function does a "fast" critical region protection and returns
* the previous protection level. This function is only called during very short
* critical regions. An embedded system which supports ISR-based drivers might
* want to implement this function by disabling interrupts. Task-based systems
* might want to implement this by using a mutex or disabling tasking. This
* function should support recursive calls from the same task or interrupt. In
* other words, sys_arch_protect() could be called while already protected. In
* that case the return value indicates that it is already protected.
* sys_arch_protect() is only required if your port is supporting an operating
* system.
*/
sys_prot_t
sys_arch_protect()
{
sys_prot_t cur;
#ifdef __MICROBLAZE__
cur = mfmsr();
mtmsr(cur & ~0x2);
#elif __PPC__
cur = mfmsr();
mtmsr(cur & ~XEXC_ALL);
#elif __arm__
cur = mfcpsr();
mtcpsr(cur & ~XIL_EXCEPTION_IRQ);
#endif
return cur;
}
/*
* This optional function does a "fast" critical region protection and returns
* the previous protection level. This function is only called during very short
* critical regions. An embedded system which supports ISR-based drivers might
* want to implement this function by disabling interrupts. Task-based systems
* might want to implement this by using a mutex or disabling tasking. This
* function should support recursive calls from the same task or interrupt. In
* other words, sys_arch_protect() could be called while already protected. In
* that case the return value indicates that it is already protected.
* sys_arch_protect() is only required if your port is supporting an operating
* system.
*/
sys_prot_t
sys_arch_protect()
{
sys_prot_t cur;
#ifdef __MICROBLAZE__
cur = mfmsr();
mtmsr(cur & ~0x2);
#elif __PPC__
cur = mfmsr();
mtmsr(cur & ~XEXC_ALL);
#elif __arm__
#ifdef PEEP
EmacDisableIntr();
#else
cur = mfcpsr();
mtcpsr(cur | 0xC0);
#endif
#endif
return cur;
}
/****************************************************************************
*
* Invalidate the entire Data cache.
*
* @param None.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void Xil_DCacheInvalidate(void)
{
u32 currmask;
u32 stack_start,stack_end,stack_size;
currmask = mfcpsr();
mtcpsr(currmask | IRQ_FIQ_MASK);
stack_end = (u32 )&_stack_end;
stack_start = (u32 )&__undef_stack;
stack_size = stack_start-stack_end;
/* Flush stack memory to save return address */
Xil_DCacheFlushRange(stack_end, stack_size);
mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
/*invalidate all D cache*/
mtcp(XREG_CP15_INVAL_DC_ALL, 0);
mtcpsr(currmask);
}
/****************************************************************************
*
* Invalidate the Data cache for the given address range.
* If the bytes specified by the address (adr) are cached by the Data cache,
* the cacheline containing that byte is invalidated. If the cacheline
* is modified (dirty), the modified contents are lost and are NOT
* written to system memory before the line is invalidated.
*
* @param Start address of range to be invalidated.
* @param Length of range to be invalidated in bytes.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
{
const u32 cacheline = 32U;
u32 end;
u32 tempadr = adr;
u32 tempend;
u32 currmask;
currmask = mfcpsr();
mtcpsr(currmask | IRQ_FIQ_MASK);
if (len != 0U) {
end = tempadr + len;
tempend = end;
/* Select L1 Data cache in CSSR */
mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
if ((tempadr & (cacheline-1U)) != 0U) {
tempadr &= (~(cacheline - 1U));
Xil_DCacheFlushLine(tempadr);
}
if ((tempend & (cacheline-1U)) != 0U) {
tempend &= (~(cacheline - 1U));
Xil_DCacheFlushLine(tempend);
}
while (tempadr < tempend) {
/* Invalidate Data cache line */
__asm__ __volatile__("mcr " \
XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (tempadr));
tempadr += cacheline;
}
}
XStatus emacps_sgsend(xemacpsif_s *xemacpsif, struct pbuf *p)
{
struct pbuf *q;
s32_t n_pbufs;
XEmacPs_Bd *txbdset, *txbd, *last_txbd = NULL;
XEmacPs_Bd *temp_txbd;
XStatus status;
XEmacPs_BdRing *txring;
u32_t bdindex;
u32_t lev;
lev = mfcpsr();
mtcpsr(lev | 0x000000C0);
txring = &(XEmacPs_GetTxRing(&xemacpsif->emacps));
/* first count the number of pbufs */
for (q = p, n_pbufs = 0; q != NULL; q = q->next)
n_pbufs++;
/* obtain as many BD's */
status = XEmacPs_BdRingAlloc(txring, n_pbufs, &txbdset);
if (status != XST_SUCCESS) {
mtcpsr(lev);
LWIP_DEBUGF(NETIF_DEBUG, ("sgsend: Error allocating TxBD\r\n"));
return XST_FAILURE;
}
for(q = p, txbd = txbdset; q != NULL; q = q->next) {
bdindex = XEMACPS_BD_TO_INDEX(txring, txbd);
if (tx_pbufs_storage[bdindex] != 0) {
mtcpsr(lev);
LWIP_DEBUGF(NETIF_DEBUG, ("PBUFS not available\r\n"));
return XST_FAILURE;
}
/* Send the data from the pbuf to the interface, one pbuf at a
time. The size of the data in each pbuf is kept in the ->len
variable. */
Xil_DCacheFlushRange((u32_t)q->payload, (u32_t)q->len);
XEmacPs_BdSetAddressTx(txbd, (u32)q->payload);
if (q->len > (XEMACPS_MAX_FRAME_SIZE - 18))
XEmacPs_BdSetLength(txbd, (XEMACPS_MAX_FRAME_SIZE - 18) & 0x3FFF);
else
XEmacPs_BdSetLength(txbd, q->len & 0x3FFF);
tx_pbufs_storage[bdindex] = (s32_t)q;
pbuf_ref(q);
last_txbd = txbd;
XEmacPs_BdClearLast(txbd);
txbd = XEmacPs_BdRingNext(txring, txbd);
}
XEmacPs_BdSetLast(last_txbd);
/* For fragmented packets, remember the 1st BD allocated for the 1st
packet fragment. The used bit for this BD should be cleared at the end
after clearing out used bits for other fragments. For packets without
just remember the allocated BD. */
temp_txbd = txbdset;
txbd = txbdset;
txbd = XEmacPs_BdRingNext(txring, txbd);
q = p->next;
for(; q != NULL; q = q->next) {
XEmacPs_BdClearTxUsed(txbd);
txbd = XEmacPs_BdRingNext(txring, txbd);
}
XEmacPs_BdClearTxUsed(temp_txbd);
status = XEmacPs_BdRingToHw(txring, n_pbufs, txbdset);
if (status != XST_SUCCESS) {
mtcpsr(lev);
LWIP_DEBUGF(NETIF_DEBUG, ("sgsend: Error submitting TxBD\r\n"));
return XST_FAILURE;
}
/* Start transmit */
XEmacPs_WriteReg((xemacpsif->emacps).Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET,
(XEmacPs_ReadReg((xemacpsif->emacps).Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK));
mtcpsr(lev);
return status;
}
/****************************************************************************
*
* Invalidate the Data cache for the given address range.
* If the bytes specified by the address (adr) are cached by the Data cache,
* the cacheline containing that byte is invalidated. If the cacheline
* is modified (dirty), the modified contents are lost and are NOT
* written to system memory before the line is invalidated.
*
* In this function, if start address or end address is not aligned to cache-line,
* particular cache-line containing unaligned start or end address is flush first
* and then invalidated the others as invalidating the same unaligned cache line
* may result into loss of data. This issue raises few possibilities.
*
*
* If the address to be invalidated is not cache-line aligned, the
* following choices are available:
* 1) Invalidate the cache line when required and do not bother much for the
* side effects. Though it sounds good, it can result in hard-to-debug issues.
* The problem is, if some other variable are allocated in the
* same cache line and had been recently updated (in cache), the invalidation
* would result in loss of data.
*
* 2) Flush the cache line first. This will ensure that if any other variable
* present in the same cache line and updated recently are flushed out to memory.
* Then it can safely be invalidated. Again it sounds good, but this can result
* in issues. For example, when the invalidation happens
* in a typical ISR (after a DMA transfer has updated the memory), then flushing
* the cache line means, loosing data that were updated recently before the ISR
* got invoked.
*
* Linux prefers the second one. To have uniform implementation (across standalone
* and Linux), the second option is implemented.
* This being the case, follwoing needs to be taken care of:
* 1) Whenever possible, the addresses must be cache line aligned. Please nore that,
* not just start address, even the end address must be cache line aligned. If that
* is taken care of, this will always work.
* 2) Avoid situations where invalidation has to be done after the data is updated by
* peripheral/DMA directly into the memory. It is not tough to achieve (may be a bit
* risky). The common use case to do invalidation is when a DMA happens. Generally
* for such use cases, buffers can be allocated first and then start the DMA. The
* practice that needs to be followed here is, immediately after buffer allocation
* and before starting the DMA, do the invalidation. With this approach, invalidation
* need not to be done after the DMA transfer is over.
*
* This is going to always work if done carefully.
* However, the concern is, there is no guarantee that invalidate has not needed to be
* done after DMA is complete. For example, because of some reasons if the first cache
* line or last cache line (assuming the buffer in question comprises of multiple cache
* lines) are brought into cache (between the time it is invalidated and DMA completes)
* because of some speculative prefetching or reading data for a variable present
* in the same cache line, then we will have to invalidate the cache after DMA is complete.
*
*
* @param Start address of range to be invalidated.
* @param Length of range to be invalidated in bytes.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
{
const u32 cacheline = 32U;
u32 end;
u32 tempadr = adr;
u32 tempend;
u32 currmask;
volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
XPS_L2CC_CACHE_INVLD_PA_OFFSET);
currmask = mfcpsr();
mtcpsr(currmask | IRQ_FIQ_MASK);
if (len != 0U) {
end = tempadr + len;
tempend = end;
/* Select L1 Data cache in CSSR */
mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
if ((tempadr & (cacheline-1U)) != 0U) {
tempadr &= (~(cacheline - 1U));
Xil_L1DCacheFlushLine(tempadr);
#ifndef USE_AMP
/* Disable Write-back and line fills */
Xil_L2WriteDebugCtrl(0x3U);
Xil_L2CacheFlushLine(tempadr);
/* Enable Write-back and line fills */
Xil_L2WriteDebugCtrl(0x0U);
Xil_L2CacheSync();
#endif
tempadr += cacheline;
}
if ((tempend & (cacheline-1U)) != 0U) {
tempend &= (~(cacheline - 1U));
Xil_L1DCacheFlushLine(tempend);
#ifndef USE_AMP
/* Disable Write-back and line fills */
Xil_L2WriteDebugCtrl(0x3U);
Xil_L2CacheFlushLine(tempend);
/* Enable Write-back and line fills */
Xil_L2WriteDebugCtrl(0x0U);
Xil_L2CacheSync();
#endif
}
while (tempadr < tempend) {
#ifndef USE_AMP
/* Invalidate L2 cache line */
*L2CCOffset = tempadr;
Xil_L2CacheSync();
#endif
#ifdef __GNUC__
/* Invalidate L1 Data cache line */
__asm__ __volatile__("mcr " \
XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (tempadr));
#elif defined (__ICCARM__)
__asm volatile ("mcr " \
XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (tempadr));
#else
{ volatile register u32 Reg
__asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
Reg = tempadr; }
#endif
tempadr += cacheline;
}
}
XStatus emacps_sgsend(xemacpsif_s *xemacpsif, struct pbuf *p)
{
struct pbuf *q;
int n_pbufs;
XEmacPs_Bd *txbdset, *txbd, *last_txbd = NULL;
XStatus Status;
XEmacPs_BdRing *txring;
unsigned int BdIndex;
unsigned int lev;
lev = mfcpsr();
mtcpsr(lev | 0x000000C0);
#ifdef PEEP
while((XEmacPs_ReadReg((xemacpsif->emacps).Config.BaseAddress,
XEMACPS_TXSR_OFFSET)) & 0x08);
#endif
txring = &(XEmacPs_GetTxRing(&xemacpsif->emacps));
/* first count the number of pbufs */
for (q = p, n_pbufs = 0; q != NULL; q = q->next)
n_pbufs++;
/* obtain as many BD's */
Status = XEmacPs_BdRingAlloc(txring, n_pbufs, &txbdset);
if (Status != XST_SUCCESS) {
mtcpsr(lev);
LWIP_DEBUGF(NETIF_DEBUG, ("sgsend: Error allocating TxBD\r\n"));
return ERR_IF;
}
for(q = p, txbd = txbdset; q != NULL; q = q->next) {
BdIndex = XEMACPS_BD_TO_INDEX(txring, txbd);
if (tx_pbufs_storage[BdIndex] != 0) {
mtcpsr(lev);
LWIP_DEBUGF(NETIF_DEBUG, ("PBUFS not available\r\n"));
return ERR_IF;
}
/* Send the data from the pbuf to the interface, one pbuf at a
time. The size of the data in each pbuf is kept in the ->len
variable. */
Xil_DCacheFlushRange((unsigned int)q->payload, (unsigned)q->len);
XEmacPs_BdSetAddressTx(txbd, (u32)q->payload);
if (q->len > (XEMACPS_MAX_FRAME_SIZE - 18))
XEmacPs_BdSetLength(txbd, (XEMACPS_MAX_FRAME_SIZE - 18) & 0x3FFF);
else
XEmacPs_BdSetLength(txbd, q->len & 0x3FFF);
tx_pbufs_storage[BdIndex] = (int)q;
pbuf_ref(q);
last_txbd = txbd;
XEmacPs_BdClearLast(txbd);
dsb();
txbd = XEmacPs_BdRingNext(txring, txbd);
}
XEmacPs_BdSetLast(last_txbd);
dsb();
for(q = p, txbd = txbdset; q != NULL; q = q->next) {
XEmacPs_BdClearTxUsed(txbd);
txbd = XEmacPs_BdRingNext(txring, txbd);
}
dsb();
Status = XEmacPs_BdRingToHw(txring, n_pbufs, txbdset);
if (Status != XST_SUCCESS) {
mtcpsr(lev);
LWIP_DEBUGF(NETIF_DEBUG, ("sgsend: Error submitting TxBD\r\n"));
return ERR_IF;
}
dsb();
/* Start transmit */
XEmacPs_WriteReg((xemacpsif->emacps).Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET,
(XEmacPs_ReadReg((xemacpsif->emacps).Config.BaseAddress,
XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK));
dsb();
mtcpsr(lev);
return Status;
}
