static void __delay(u64 ticks)
{
u64 start = mftb();
while (mftb() - start < ticks)
;
}
static void TimerWait(unsigned long duration)
{
unsigned long end = mftb() + duration;
while(TBCompare(mftb(), end) != TB_AAFTERB)
PpcCpuRelax();
}
static void tdelay(uint64_t i)
{
uint64_t t = mftb();
t += i;
while (mftb() < t) asm volatile("or 31,31,31");
asm volatile("or 2,2,2");
}
bool GuiTrigger::Down() {
u32 wiibtn = WPAD_BUTTON_DOWN;
if ((wpad->btns_d | wpad->btns_h) & (wiibtn | WPAD_CLASSIC_BUTTON_DOWN)
|| (pad.btns_d | pad.btns_h) & PAD_BUTTON_DOWN
|| pad.stickY < -PADCAL
|| WPAD_StickY(0) < -PADCAL) {
if (wpad->btns_d & (wiibtn | WPAD_CLASSIC_BUTTON_DOWN)
|| pad.btns_d & PAD_BUTTON_DOWN) {
prev[chan] = mftb();
_delay[chan] = SCROLL_DELAY_INITIAL; // reset scroll _delay
return true;
}
now[chan] = mftb();
if (_diff_usec(prev[chan], now[chan]) > _delay[chan]) {
prev[chan] = now[chan];
if (_delay[chan] == SCROLL_DELAY_INITIAL)
_delay[chan] = SCROLL_DELAY_LOOP;
else if (_delay[chan] > SCROLL_DELAY_DECREASE)
_delay[chan] -= SCROLL_DELAY_DECREASE;
return true;
}
}
return false;
}
void calculate_speed(void* dst, u32 len, u32 *speed)
{
tb_t start, end;
mftb(&start);
device_frag_read(dst, len, 0);
mftb(&end);
*speed = tb_diff_usec(&end, &start);
}
void
delay(int usecs)
{
uint64_t tb,ttb;
tb = mftb();
ttb = tb + howmany(usecs * 1000, ns_per_tick);
while (tb < ttb)
tb = mftb();
}
void
delay(int usecs)
{
uint64_t tb,ttb;
tb = mftb();
ttb = tb + (usecs * 1000 + ns_per_tick - 1) / ns_per_tick;
while (tb < ttb)
tb = mftb();
}
void network_init()
{
struct ip_addr ipaddr, netmask, gw;
printf("trying to initialize network...\n");
#ifdef STATS
stats_init();
#endif /* STATS */
mem_init();
memp_init();
pbuf_init();
netif_init();
ip_init();
udp_init();
tcp_init();
etharp_init();
printf("ok now the NIC\n");
if (!netif_add(&netif, &ipaddr, &netmask, &gw, NULL, enet_init, ip_input))
{
printf("netif_add failed!\n");
return;
}
netif_set_default(&netif);
dhcp_start(&netif);
mftb(&last_tcp);
mftb(&last_dhcp);
printf("\nWaiting for DHCP");
int i;
for (i=0; i<10; i++) {
mdelay(500);
network_poll();
printf(".");
if (netif.ip_addr.addr)
break;
}
if (netif.ip_addr.addr) {
printf("%u.%u.%u.%u\n",
(netif.ip_addr.addr >> 24) & 0xFF,
(netif.ip_addr.addr >> 16) & 0xFF,
(netif.ip_addr.addr >> 8) & 0xFF,
(netif.ip_addr.addr >> 0) & 0xFF);
printf("\n");
} else {
void mdelay(unsigned int ms)
{
tb_t start, end;
mftb(&start);
while (1)
{
mftb(&end);
if (tb_diff_msec(&end, &start) >= ms)
break;
}
}
void load_sprs(struct vcpu *v)
{
ulong timebase_delta;
mtsprg0(v->arch.sprg[0]);
mtsprg1(v->arch.sprg[1]);
mtsprg2(v->arch.sprg[2]);
mtsprg3(v->arch.sprg[3]);
mtdar(v->arch.dar);
mtdsisr(v->arch.dsisr);
if (v->arch.pmu_enabled) {
if (v->arch.perf_sprs_stored)
load_pmc_sprs(&(v->arch.perf_sprs));
else
load_pmc_sprs(&perf_clear_sprs);
}
load_cpu_sprs(v);
/* adjust the DEC value to account for cycles while not
* running this OS */
timebase_delta = mftb() - v->arch.timebase;
if (timebase_delta > v->arch.dec)
v->arch.dec = 0;
else
v->arch.dec -= timebase_delta;
}
static long pSeries_lpar_hpte_remove(unsigned long hpte_group)
{
unsigned long slot_offset;
unsigned long lpar_rc;
int i;
unsigned long dummy1, dummy2;
/* pick a random slot to start at */
slot_offset = mftb() & 0x7;
for (i = 0; i < HPTES_PER_GROUP; i++) {
/* don't remove a bolted entry */
lpar_rc = plpar_pte_remove(H_ANDCOND, hpte_group + slot_offset,
(0x1UL << 4), &dummy1, &dummy2);
if (lpar_rc == H_SUCCESS)
return i;
/*
* The test for adjunct partition is performed before the
* ANDCOND test. H_RESOURCE may be returned, so we need to
* check for that as well.
*/
BUG_ON(lpar_rc != H_NOT_FOUND && lpar_rc != H_RESOURCE);
slot_offset++;
slot_offset &= 0x7;
}
return -1;
}
void
sys_init(void)
{
timeouts.next = NULL;
mftb(&startTime);
return;
}
void p8_sbe_init_timer(void)
{
struct dt_node *np;
int64_t rc;
uint32_t tick_us;
np = dt_find_compatible_node(dt_root, NULL, "ibm,power8-sbe-timer");
if (!np)
return;
sbe_timer_chip = dt_get_chip_id(np);
tick_us = dt_prop_get_u32(np, "tick-time-us");
sbe_timer_inc = usecs_to_tb(tick_us);
sbe_timer_target = ~0ull;
rc = xscom_read(sbe_timer_chip, 0xE0006, &sbe_last_gen);
if (rc) {
prerror("SLW: Error %lld reading tmr gen count\n", rc);
return;
}
sbe_last_gen_stamp = mftb();
prlog(PR_INFO, "SLW: Timer facility on chip %d, resolution %dus\n",
sbe_timer_chip, tick_us);
sbe_has_timer = true;
}
static long iSeries_hpte_remove(unsigned long hpte_group)
{
unsigned long slot_offset;
int i;
HPTE lhpte;
/* Pick a random slot to start at */
slot_offset = mftb() & 0x7;
iSeries_hlock(hpte_group);
for (i = 0; i < HPTES_PER_GROUP; i++) {
lhpte.dw0.dword0 =
iSeries_hpte_getword0(hpte_group + slot_offset);
if (!lhpte.dw0.dw0.bolted) {
HvCallHpt_invalidateSetSwBitsGet(hpte_group +
slot_offset, 0, 0);
iSeries_hunlock(hpte_group);
return i;
}
slot_offset++;
slot_offset &= 0x7;
}
iSeries_hunlock(hpte_group);
return -1;
}
/*
* Routine: cpu_machine_init
* Function:
*/
void
cpu_machine_init(
void)
{
struct per_proc_info *proc_info;
volatile struct per_proc_info *mproc_info;
proc_info = getPerProc();
mproc_info = PerProcTable[master_cpu].ppe_vaddr;
if (proc_info != mproc_info) {
simple_lock(&rht_lock);
if (rht_state & RHT_WAIT)
thread_wakeup(&rht_state);
rht_state &= ~(RHT_BUSY|RHT_WAIT);
simple_unlock(&rht_lock);
}
PE_cpu_machine_init(proc_info->cpu_id, !(proc_info->cpu_flags & BootDone));
if (proc_info->hibernate) {
uint32_t tbu, tbl;
do {
tbu = mftbu();
tbl = mftb();
} while (mftbu() != tbu);
proc_info->hibernate = 0;
hibernate_machine_init();
// hibernate_machine_init() could take minutes and we don't want timeouts
// to fire as soon as scheduling starts. Reset timebase so it appears
// no time has elapsed, as it would for regular sleep.
mttb(0);
mttbu(tbu);
mttb(tbl);
}
if (proc_info != mproc_info) {
while (!((mproc_info->cpu_flags) & SignalReady))
continue;
cpu_sync_timebase();
}
ml_init_interrupt();
if (proc_info != mproc_info)
simple_lock(&SignalReadyLock);
proc_info->cpu_flags |= BootDone|SignalReady;
if (proc_info != mproc_info) {
if (proc_info->ppXFlags & SignalReadyWait) {
(void)hw_atomic_and(&proc_info->ppXFlags, ~SignalReadyWait);
thread_wakeup(&proc_info->cpu_flags);
}
simple_unlock(&SignalReadyLock);
pmsPark(); /* Timers should be cool now, park the power management stepper */
}
}
unsigned long timeGetTime() {
/*
struct timeval tv;
gettimeofday(&tv, 0); // well, maybe there are better ways
return tv.tv_sec * 100000 + tv.tv_usec / 10; // to do that, but at least it works
*/
return mftb()/(PPC_TIMEBASE_FREQ/100000);
}
/**
Retrieves the current value of a 64-bit free running performance counter.
The counter can either count up by 1 or count down by 1. If the physical
performance counter counts by a larger increment, then the counter values
must be translated. The properties of the counter can be retrieved from
GetPerformanceCounterProperties().
@return The current value of the free running performance counter.
**/
UINT64
EFIAPI
GetPerformanceCounter (
VOID
)
{
// Just return the value of system count
return mftb ();
}
void
md_presync_timebase(volatile struct cpu_hatch_data *h)
{
uint64_t tb;
/* Sync timebase. */
tb = mftb();
tb += 100000; /* 3ms @ 33MHz */
h->tbu = tb >> 32;
h->tbl = tb & 0xffffffff;
while (tb > mftb())
;
__asm volatile ("sync; isync");
h->running = 0;
delay(500000);
}
static inline ulong time_from_shared(void)
{
ulong t;
DBG("tb_freq: %ld\n", ppc_tb_freq);
t = mftb() - HYPERVISOR_shared_info->arch.boot_timebase;
t /= ppc_tb_freq;
t += HYPERVISOR_shared_info->wc_sec;
return t;
}
void trace_add(union trace *trace, u8 type, u16 len)
{
struct trace_info *ti = this_cpu()->trace;
unsigned int tsz;
trace->hdr.type = type;
trace->hdr.len_div_8 = (len + 7) >> 3;
tsz = trace->hdr.len_div_8 << 3;
#ifdef DEBUG_TRACES
assert(tsz >= sizeof(trace->hdr));
assert(tsz <= sizeof(*trace));
assert(trace->hdr.type != TRACE_REPEAT);
assert(trace->hdr.type != TRACE_OVERFLOW);
#endif
/* Skip traces not enabled in the debug descriptor */
if (!((1ul << trace->hdr.type) & debug_descriptor.trace_mask))
return;
trace->hdr.timestamp = cpu_to_be64(mftb());
trace->hdr.cpu = cpu_to_be16(this_cpu()->server_no);
lock(&ti->lock);
/* Throw away old entries before we overwrite them. */
while ((be64_to_cpu(ti->tb.start) + be64_to_cpu(ti->tb.mask) + 1)
< (be64_to_cpu(ti->tb.end) + tsz)) {
struct trace_hdr *hdr;
hdr = (void *)ti->tb.buf +
be64_to_cpu(ti->tb.start & ti->tb.mask);
ti->tb.start = cpu_to_be64(be64_to_cpu(ti->tb.start) +
(hdr->len_div_8 << 3));
}
/* Must update ->start before we rewrite new entries. */
lwsync(); /* write barrier */
/* Check for duplicates... */
if (!handle_repeat(&ti->tb, trace)) {
/* This may go off end, and that's why ti->tb.buf is oversize */
memcpy(ti->tb.buf + be64_to_cpu(ti->tb.end & ti->tb.mask),
trace, tsz);
ti->tb.last = ti->tb.end;
lwsync(); /* write barrier: write entry before exposing */
ti->tb.end = cpu_to_be64(be64_to_cpu(ti->tb.end) + tsz);
}
unlock(&ti->lock);
}
static void ShowFPS() {
static unsigned long lastTick = 0;
static int frames = 0;
unsigned long nowTick;
frames++;
nowTick = mftb() / (PPC_TIMEBASE_FREQ / 1000);
if (lastTick + 1000 <= nowTick) {
printf("Gl %d fps\r\n", frames);
frames = 0;
lastTick = nowTick;
}
}
static unsigned long __init xen_get_boot_time(void)
{
ulong t;
if (is_initial_xendomain()) {
t = host_md_get_boot_time();
HYPERVISOR_shared_info->wc_sec = t;
HYPERVISOR_shared_info->arch.boot_timebase = mftb();
DBG("%s: time: %ld\n", __func__, t);
} else {
t = time_from_shared();
DBG("%s: %ld\n", __func__, t);
}
return t;
}
static int xen_set_rtc_time(struct rtc_time *tm)
{
ulong sec;
if (is_initial_xendomain()) {
host_md_set_rtc_time(tm);
return 0;
}
sec = mktime(tm->tm_year, tm->tm_mon, tm->tm_mday,
tm->tm_hour, tm->tm_min, tm->tm_sec);
HYPERVISOR_shared_info->wc_sec = sec;
HYPERVISOR_shared_info->arch.boot_timebase = mftb();
return 0;
}
void save_sprs(struct vcpu *v)
{
v->arch.timebase = mftb();
v->arch.sprg[0] = mfsprg0();
v->arch.sprg[1] = mfsprg1();
v->arch.sprg[2] = mfsprg2();
v->arch.sprg[3] = mfsprg3();
v->arch.dar = mfdar();
v->arch.dsisr = mfdsisr();
if (v->arch.pmu_enabled) {
save_pmc_sprs(&(v->arch.perf_sprs));
v->arch.perf_sprs_stored = 1;
}
save_cpu_sprs(v);
}
// Returns current time in milliseconds
unsigned int GetTimerMS(void)
{
return mftb()/(PPC_TIMEBASE_FREQ/1000);
}
static inline uint64_t xenon_time(){
return mftb()/PPC_TIMEBASE_FREQ;
}
/** Returns the current time in milliseconds,
* may be the same as sys_jiffies or at least based on it. */
u32_t sys_now(void)
{
tb_t now;
mftb(&now);
return (u32_t) tb_diff_msec(&now, &startTime);
}
int
main(void)
{
uint64_t maxmem = 0;
void *heapbase;
int i, err;
struct ps3_devdesc currdev;
struct open_file f;
lv1_get_physmem(&maxmem);
ps3mmu_init(maxmem);
/*
* Set up console.
*/
cons_probe();
/*
* Set the heap to one page after the end of the loader.
*/
heapbase = (void *)(maxmem - 0x80000);
setheap(heapbase, maxmem);
/*
* March through the device switch probing for things.
*/
for (i = 0; devsw[i] != NULL; i++) {
if (devsw[i]->dv_init != NULL) {
err = (devsw[i]->dv_init)();
if (err) {
printf("\n%s: initialization failed err=%d\n",
devsw[i]->dv_name, err);
continue;
}
}
currdev.d_dev = devsw[i];
currdev.d_type = currdev.d_dev->dv_type;
if (strcmp(devsw[i]->dv_name, "cd") == 0) {
f.f_devdata = &currdev;
currdev.d_unit = 0;
if (devsw[i]->dv_open(&f, &currdev) == 0)
break;
}
if (strcmp(devsw[i]->dv_name, "disk") == 0) {
f.f_devdata = &currdev;
currdev.d_unit = 3;
currdev.d_disk.pnum = 1;
currdev.d_disk.ptype = PTYPE_GPT;
if (devsw[i]->dv_open(&f, &currdev) == 0)
break;
}
if (strcmp(devsw[i]->dv_name, "net") == 0)
break;
}
if (devsw[i] == NULL)
panic("No boot device found!");
else
printf("Boot device: %s\n", devsw[i]->dv_name);
/*
* Get timebase at boot.
*/
basetb = mftb();
archsw.arch_getdev = ps3_getdev;
archsw.arch_copyin = ps3_copyin;
archsw.arch_copyout = ps3_copyout;
archsw.arch_readin = ps3_readin;
archsw.arch_autoload = ps3_autoload;
printf("\n");
printf("%s, Revision %s\n", bootprog_name, bootprog_rev);
printf("(%s, %s)\n", bootprog_maker, bootprog_date);
printf("Memory: %lldKB\n", maxmem / 1024);
env_setenv("currdev", EV_VOLATILE, ps3_fmtdev(&currdev),
ps3_setcurrdev, env_nounset);
env_setenv("loaddev", EV_VOLATILE, ps3_fmtdev(&currdev), env_noset,
env_nounset);
setenv("LINES", "24", 1);
setenv("hw.platform", "ps3", 1);
interact(); /* doesn't return */
return (0);
}
int
getsecs()
{
return ((mftb() - basetb)*ns_per_tick/1000000000);
}
void
MainMenu (int selectedMenu)
{
tb_t start,end;
mftb(&start);
int quit = 0;
int ret;
#ifdef HW_RVL
// don't show dvd motor off on the wii
menuitems[5][0] = 0;
// rename reset/exit items
sprintf (menuitems[6], "Return to Wii Menu");
sprintf (menuitems[7], "Return to Homebrew Channel");
#endif
// disable game-specific menu items if a ROM isn't loaded
if (!ROMLoaded)
menuitems[3][0] = '\0';
else
sprintf (menuitems[3], "Game Menu");
VIDEO_WaitVSync ();
while (quit == 0)
{
if(selectedMenu >= 0)
{
ret = selectedMenu;
selectedMenu = -1; // default back to main menu
}
else
{
ret = RunMenu (menuitems, menucount, (char*)"Main Menu");
}
switch (ret)
{
case 0:
// Load ROM Menu
quit = LoadManager ();
break;
case 1:
// Configure Controllers
ConfigureControllers ();
break;
case 2:
// Preferences
PreferencesMenu ();
break;
case 3:
// Game Options
quit = GameMenu ();
break;
case 4:
// Credits
Credits ();
WaitButtonA ();
break;
case 5:
// turn the dvd motor off (GC only)
#ifdef HW_DOL
dvd_motor_off ();
#endif
case 6:
// Reset the Gamecube/Wii
Reboot();
break;
case 7:
ExitToLoader();
break;
case -1: // Button B
// Return to Game
if(ROMLoaded)
quit = 1;
break;
}
}
// Wait for buttons to be released
int count = 0; // how long we've been waiting for the user to release the button
while(count < 50 && (
PAD_ButtonsHeld(0)
#ifdef HW_RVL
|| WPAD_ButtonsHeld(0)
#endif
))
{
VIDEO_WaitVSync();
count++;
}
mftb(&end);
loadtimeradjust += tb_diff_msec(&end, &start);
}