enum MHI_STATUS mhi_test_for_device_ready(struct mhi_device_ctxt *mhi_dev_ctxt)
{
u32 pcie_word_val = 0;
u32 expiry_counter;
mhi_log(MHI_MSG_INFO, "Waiting for MMIO Ready bit to be set\n");
/* Read MMIO and poll for READY bit to be set */
pcie_word_val = mhi_reg_read(mhi_dev_ctxt->mmio_addr, MHISTATUS);
MHI_READ_FIELD(pcie_word_val,
MHISTATUS_READY_MASK,
MHISTATUS_READY_SHIFT);
if (pcie_word_val == 0xFFFFFFFF)
return MHI_STATUS_LINK_DOWN;
expiry_counter = 0;
while (MHI_STATE_READY != pcie_word_val && expiry_counter < 50) {
expiry_counter++;
mhi_log(MHI_MSG_ERROR,
"Device is not ready, sleeping and retrying.\n");
msleep(MHI_READY_STATUS_TIMEOUT_MS);
pcie_word_val = mhi_reg_read(mhi_dev_ctxt->mmio_addr,
MHISTATUS);
MHI_READ_FIELD(pcie_word_val,
MHISTATUS_READY_MASK, MHISTATUS_READY_SHIFT);
}
if (pcie_word_val != MHI_STATE_READY)
return MHI_STATUS_DEVICE_NOT_READY;
return MHI_STATUS_SUCCESS;
}
int bhi_probe(struct mhi_pcie_dev_info *mhi_pcie_device)
{
struct bhi_ctxt_t *bhi_ctxt = &mhi_pcie_device->bhi_ctxt;
enum MHI_STATUS ret_val = MHI_STATUS_SUCCESS;
u32 pcie_word_val = 0;
int r;
if (NULL == mhi_pcie_device || 0 == mhi_pcie_device->core.bar0_base
|| 0 == mhi_pcie_device->core.bar0_end)
return -EIO;
bhi_ctxt->bhi_base = mhi_pcie_device->core.bar0_base;
pcie_word_val = mhi_reg_read(bhi_ctxt->bhi_base, BHIOFF);
bhi_ctxt->bhi_base += pcie_word_val;
mhi_log(MHI_MSG_INFO,
"Successfully registered char dev. bhi base is: 0x%p.\n",
bhi_ctxt->bhi_base);
ret_val = alloc_chrdev_region(&bhi_ctxt->bhi_dev, 0, 1, "bhi");
if (IS_ERR_VALUE(ret_val)) {
mhi_log(MHI_MSG_CRITICAL,
"Failed to alloc char device %d\n",
ret_val);
return -EIO;
}
bhi_ctxt->bhi_class = class_create(THIS_MODULE, "bhi");
if (IS_ERR(bhi_ctxt->bhi_class)) {
mhi_log(MHI_MSG_CRITICAL,
"Failed to instantiate class %d\n",
ret_val);
r = PTR_RET(bhi_ctxt->bhi_class);
goto err_class_create;
}
cdev_init(&bhi_ctxt->cdev, &bhi_fops);
bhi_ctxt->cdev.owner = THIS_MODULE;
ret_val = cdev_add(&bhi_ctxt->cdev, bhi_ctxt->bhi_dev, 1);
bhi_ctxt->dev = device_create(bhi_ctxt->bhi_class, NULL,
bhi_ctxt->bhi_dev, NULL,
"bhi");
if (IS_ERR(bhi_ctxt->dev)) {
mhi_log(MHI_MSG_CRITICAL,
"Failed to add bhi cdev\n");
r = PTR_RET(bhi_ctxt->dev);
goto err_dev_create;
}
return 0;
err_dev_create:
cdev_del(&bhi_ctxt->cdev);
class_destroy(bhi_ctxt->bhi_class);
err_class_create:
unregister_chrdev_region(MAJOR(bhi_ctxt->bhi_dev), 1);
return r;
}
static inline void mhi_set_m_state(struct mhi_device_ctxt *mhi_dev_ctxt,
enum MHI_STATE new_state)
{
if (MHI_STATE_RESET == new_state) {
mhi_reg_write_field(mhi_dev_ctxt,
mhi_dev_ctxt->mmio_info.mmio_addr, MHICTRL,
MHICTRL_RESET_MASK,
MHICTRL_RESET_SHIFT,
1);
} else {
mhi_reg_write_field(mhi_dev_ctxt,
mhi_dev_ctxt->mmio_info.mmio_addr, MHICTRL,
MHICTRL_MHISTATE_MASK,
MHICTRL_MHISTATE_SHIFT,
new_state);
}
mhi_reg_read(mhi_dev_ctxt->mmio_info.mmio_addr, MHICTRL);
}
enum MHI_STATUS mhi_init_mmio(struct mhi_device_ctxt *mhi_dev_ctxt)
{
u64 pcie_dword_val = 0;
u32 pcie_word_val = 0;
u32 i = 0;
enum MHI_STATUS ret_val;
mhi_log(MHI_MSG_INFO, "~~~ Initializing MMIO ~~~\n");
mhi_dev_ctxt->mmio_addr = mhi_dev_ctxt->dev_props->bar0_base;
mhi_log(MHI_MSG_INFO, "Bar 0 address is at: 0x%p\n",
mhi_dev_ctxt->mmio_addr);
mhi_dev_ctxt->mmio_len = mhi_reg_read(mhi_dev_ctxt->mmio_addr,
MHIREGLEN);
if (0 == mhi_dev_ctxt->mmio_len) {
mhi_log(MHI_MSG_ERROR, "Received mmio length as zero\n");
return MHI_STATUS_ERROR;
}
mhi_log(MHI_MSG_INFO, "Testing MHI Ver\n");
mhi_dev_ctxt->dev_props->mhi_ver = mhi_reg_read(
mhi_dev_ctxt->mmio_addr, MHIVER);
if (MHI_VERSION != mhi_dev_ctxt->dev_props->mhi_ver) {
mhi_log(MHI_MSG_CRITICAL, "Bad MMIO version, 0x%x\n",
mhi_dev_ctxt->dev_props->mhi_ver);
if (mhi_dev_ctxt->dev_props->mhi_ver == 0xFFFFFFFF)
ret_val = mhi_wait_for_mdm(mhi_dev_ctxt);
if (ret_val)
return MHI_STATUS_ERROR;
}
/* Enable the channels */
for (i = 0; i < MHI_MAX_CHANNELS; ++i) {
struct mhi_chan_ctxt *chan_ctxt =
&mhi_dev_ctxt->mhi_ctrl_seg->mhi_cc_list[i];
if (VALID_CHAN_NR(i))
chan_ctxt->mhi_chan_state = MHI_CHAN_STATE_ENABLED;
else
chan_ctxt->mhi_chan_state = MHI_CHAN_STATE_DISABLED;
}
mhi_log(MHI_MSG_INFO,
"Read back MMIO Ready bit successfully. Moving on..\n");
mhi_log(MHI_MSG_INFO, "Reading channel doorbell offset\n");
mhi_dev_ctxt->channel_db_addr = mhi_dev_ctxt->mmio_addr;
mhi_dev_ctxt->event_db_addr = mhi_dev_ctxt->mmio_addr;
mhi_dev_ctxt->channel_db_addr += mhi_reg_read_field(
mhi_dev_ctxt->mmio_addr,
CHDBOFF, CHDBOFF_CHDBOFF_MASK,
CHDBOFF_CHDBOFF_SHIFT);
mhi_log(MHI_MSG_INFO, "Reading event doorbell offset\n");
mhi_dev_ctxt->event_db_addr += mhi_reg_read_field(
mhi_dev_ctxt->mmio_addr,
ERDBOFF, ERDBOFF_ERDBOFF_MASK,
ERDBOFF_ERDBOFF_SHIFT);
mhi_log(MHI_MSG_INFO, "Setting all MMIO values.\n");
mhi_reg_write_field(mhi_dev_ctxt, mhi_dev_ctxt->mmio_addr, MHICFG,
MHICFG_NER_MASK, MHICFG_NER_SHIFT,
MHI_MAX_CHANNELS);
pcie_dword_val = mhi_v2p_addr(mhi_dev_ctxt->mhi_ctrl_seg_info,
(uintptr_t)mhi_dev_ctxt->mhi_ctrl_seg->mhi_cc_list);
pcie_word_val = HIGH_WORD(pcie_dword_val);
mhi_reg_write_field(mhi_dev_ctxt,
mhi_dev_ctxt->mmio_addr, CCABAP_HIGHER,
CCABAP_HIGHER_CCABAP_HIGHER_MASK,
CCABAP_HIGHER_CCABAP_HIGHER_SHIFT, pcie_word_val);
pcie_word_val = LOW_WORD(pcie_dword_val);
mhi_reg_write_field(mhi_dev_ctxt, mhi_dev_ctxt->mmio_addr, CCABAP_LOWER,
CCABAP_LOWER_CCABAP_LOWER_MASK,
CCABAP_LOWER_CCABAP_LOWER_SHIFT,
pcie_word_val);
/* Write the Event Context Base Address Register High and Low parts */
pcie_dword_val = mhi_v2p_addr(mhi_dev_ctxt->mhi_ctrl_seg_info,
(uintptr_t)mhi_dev_ctxt->mhi_ctrl_seg->mhi_ec_list);
pcie_word_val = HIGH_WORD(pcie_dword_val);
mhi_reg_write_field(mhi_dev_ctxt,
mhi_dev_ctxt->mmio_addr, ECABAP_HIGHER,
ECABAP_HIGHER_ECABAP_HIGHER_MASK,
ECABAP_HIGHER_ECABAP_HIGHER_SHIFT, pcie_word_val);
pcie_word_val = LOW_WORD(pcie_dword_val);
mhi_reg_write_field(mhi_dev_ctxt, mhi_dev_ctxt->mmio_addr, ECABAP_LOWER,
ECABAP_LOWER_ECABAP_LOWER_MASK,
ECABAP_LOWER_ECABAP_LOWER_SHIFT, pcie_word_val);
/* Write the Command Ring Control Register High and Low parts */
pcie_dword_val = mhi_v2p_addr(mhi_dev_ctxt->mhi_ctrl_seg_info,
(uintptr_t)mhi_dev_ctxt->mhi_ctrl_seg->mhi_cmd_ctxt_list);
pcie_word_val = HIGH_WORD(pcie_dword_val);
mhi_reg_write_field(mhi_dev_ctxt,
mhi_dev_ctxt->mmio_addr, CRCBAP_HIGHER,
CRCBAP_HIGHER_CRCBAP_HIGHER_MASK,
CRCBAP_HIGHER_CRCBAP_HIGHER_SHIFT,
pcie_word_val);
pcie_word_val = LOW_WORD(pcie_dword_val);
mhi_reg_write_field(mhi_dev_ctxt,
mhi_dev_ctxt->mmio_addr, CRCBAP_LOWER,
CRCBAP_LOWER_CRCBAP_LOWER_MASK,
CRCBAP_LOWER_CRCBAP_LOWER_SHIFT,
pcie_word_val);
mhi_dev_ctxt->cmd_db_addr = mhi_dev_ctxt->mmio_addr + CRDB_LOWER;
/* Set the control segment in the MMIO */
pcie_dword_val = mhi_v2p_addr(mhi_dev_ctxt->mhi_ctrl_seg_info,
(uintptr_t)mhi_dev_ctxt->mhi_ctrl_seg);
pcie_word_val = HIGH_WORD(pcie_dword_val);
mhi_reg_write_field(mhi_dev_ctxt,
mhi_dev_ctxt->mmio_addr, MHICTRLBASE_HIGHER,
MHICTRLBASE_HIGHER_MHICTRLBASE_HIGHER_MASK,
MHICTRLBASE_HIGHER_MHICTRLBASE_HIGHER_SHIFT,
pcie_word_val);
pcie_word_val = LOW_WORD(pcie_dword_val);
mhi_reg_write_field(mhi_dev_ctxt,
mhi_dev_ctxt->mmio_addr, MHICTRLBASE_LOWER,
MHICTRLBASE_LOWER_MHICTRLBASE_LOWER_MASK,
MHICTRLBASE_LOWER_MHICTRLBASE_LOWER_SHIFT,
pcie_word_val);
pcie_dword_val = mhi_v2p_addr(mhi_dev_ctxt->mhi_ctrl_seg_info,
(uintptr_t)mhi_dev_ctxt->mhi_ctrl_seg) +
mhi_get_memregion_len(mhi_dev_ctxt->mhi_ctrl_seg_info) - 1;
pcie_word_val = HIGH_WORD(pcie_dword_val);
mhi_reg_write_field(mhi_dev_ctxt,
mhi_dev_ctxt->mmio_addr, MHICTRLLIMIT_HIGHER,
MHICTRLLIMIT_HIGHER_MHICTRLLIMIT_HIGHER_MASK,
MHICTRLLIMIT_HIGHER_MHICTRLLIMIT_HIGHER_SHIFT,
pcie_word_val);
pcie_word_val = LOW_WORD(pcie_dword_val);
mhi_reg_write_field(mhi_dev_ctxt,
mhi_dev_ctxt->mmio_addr, MHICTRLLIMIT_LOWER,
MHICTRLLIMIT_LOWER_MHICTRLLIMIT_LOWER_MASK,
MHICTRLLIMIT_LOWER_MHICTRLLIMIT_LOWER_SHIFT,
pcie_word_val);
/* Set the data segment in the MMIO */
pcie_dword_val = MHI_DATA_SEG_WINDOW_START_ADDR;
pcie_word_val = HIGH_WORD(pcie_dword_val);
mhi_reg_write_field(mhi_dev_ctxt,
mhi_dev_ctxt->mmio_addr, MHIDATABASE_HIGHER,
MHIDATABASE_HIGHER_MHIDATABASE_HIGHER_MASK,
MHIDATABASE_HIGHER_MHIDATABASE_HIGHER_SHIFT,
pcie_word_val);
pcie_word_val = LOW_WORD(pcie_dword_val);
mhi_reg_write_field(mhi_dev_ctxt,
mhi_dev_ctxt->mmio_addr, MHIDATABASE_LOWER,
MHIDATABASE_LOWER_MHIDATABASE_LOWER_MASK,
MHIDATABASE_LOWER_MHIDATABASE_LOWER_SHIFT,
pcie_word_val);
pcie_dword_val = MHI_DATA_SEG_WINDOW_END_ADDR;
pcie_word_val = HIGH_WORD(pcie_dword_val);
mhi_reg_write_field(mhi_dev_ctxt,
mhi_dev_ctxt->mmio_addr, MHIDATALIMIT_HIGHER,
MHIDATALIMIT_HIGHER_MHIDATALIMIT_HIGHER_MASK,
MHIDATALIMIT_HIGHER_MHIDATALIMIT_HIGHER_SHIFT,
pcie_word_val);
pcie_word_val = LOW_WORD(pcie_dword_val);
mhi_reg_write_field(mhi_dev_ctxt,
mhi_dev_ctxt->mmio_addr, MHIDATALIMIT_LOWER,
MHIDATALIMIT_LOWER_MHIDATALIMIT_LOWER_MASK,
MHIDATALIMIT_LOWER_MHIDATALIMIT_LOWER_SHIFT,
pcie_word_val);
mhi_log(MHI_MSG_INFO, "Done..\n");
return MHI_STATUS_SUCCESS;
}
static ssize_t bhi_write(struct file *file,
const char __user *buf,
size_t count, loff_t *offp)
{
enum MHI_STATUS ret_val = MHI_STATUS_SUCCESS;
u32 pcie_word_val = 0;
u32 i = 0;
struct bhi_ctxt_t *bhi_ctxt =
&(((struct mhi_pcie_dev_info *)file->private_data)->bhi_ctxt);
struct mhi_device_ctxt *mhi_dev_ctxt =
&((struct mhi_pcie_dev_info *)file->private_data)->mhi_ctxt;
size_t amount_copied = 0;
uintptr_t align_len = 0x1000;
u32 tx_db_val = 0;
if (buf == NULL || 0 == count)
return -EIO;
if (count > BHI_MAX_IMAGE_SIZE)
return -ENOMEM;
wait_event_interruptible(*mhi_dev_ctxt->mhi_ev_wq.bhi_event,
mhi_dev_ctxt->mhi_state == MHI_STATE_BHI);
mhi_log(MHI_MSG_INFO, "Entered. User Image size 0x%zx\n", count);
bhi_ctxt->unaligned_image_loc = kmalloc(count + (align_len - 1),
GFP_KERNEL);
if (bhi_ctxt->unaligned_image_loc == NULL)
return -ENOMEM;
mhi_log(MHI_MSG_INFO, "Unaligned Img Loc: %p\n",
bhi_ctxt->unaligned_image_loc);
bhi_ctxt->image_loc =
(void *)((uintptr_t)bhi_ctxt->unaligned_image_loc +
(align_len - (((uintptr_t)bhi_ctxt->unaligned_image_loc) %
align_len)));
mhi_log(MHI_MSG_INFO, "Aligned Img Loc: %p\n", bhi_ctxt->image_loc);
bhi_ctxt->image_size = count;
if (0 != copy_from_user(bhi_ctxt->image_loc, buf, count)) {
ret_val = -ENOMEM;
goto bhi_copy_error;
}
amount_copied = count;
/* Flush the writes, in anticipation for a device read */
wmb();
mhi_log(MHI_MSG_INFO,
"Copied image from user at addr: %p\n", bhi_ctxt->image_loc);
bhi_ctxt->phy_image_loc = dma_map_single(
&mhi_dev_ctxt->dev_info->plat_dev->dev,
bhi_ctxt->image_loc,
bhi_ctxt->image_size,
DMA_TO_DEVICE);
if (dma_mapping_error(NULL, bhi_ctxt->phy_image_loc)) {
ret_val = -EIO;
goto bhi_copy_error;
}
mhi_log(MHI_MSG_INFO,
"Mapped image to DMA addr 0x%lx:\n",
(uintptr_t)bhi_ctxt->phy_image_loc);
bhi_ctxt->image_size = count;
/* Write the image size */
pcie_word_val = HIGH_WORD(bhi_ctxt->phy_image_loc);
mhi_reg_write_field(mhi_dev_ctxt, bhi_ctxt->bhi_base,
BHI_IMGADDR_HIGH,
0xFFFFFFFF,
0,
pcie_word_val);
pcie_word_val = LOW_WORD(bhi_ctxt->phy_image_loc);
mhi_reg_write_field(mhi_dev_ctxt, bhi_ctxt->bhi_base,
BHI_IMGADDR_LOW,
0xFFFFFFFF,
0,
pcie_word_val);
pcie_word_val = bhi_ctxt->image_size;
mhi_reg_write_field(mhi_dev_ctxt, bhi_ctxt->bhi_base, BHI_IMGSIZE,
0xFFFFFFFF, 0, pcie_word_val);
pcie_word_val = mhi_reg_read(bhi_ctxt->bhi_base, BHI_IMGTXDB);
mhi_reg_write_field(mhi_dev_ctxt, bhi_ctxt->bhi_base,
BHI_IMGTXDB, 0xFFFFFFFF, 0, ++pcie_word_val);
mhi_reg_write(mhi_dev_ctxt, bhi_ctxt->bhi_base, BHI_INTVEC, 0);
for (i = 0; i < BHI_POLL_NR_RETRIES; ++i) {
tx_db_val = mhi_reg_read_field(bhi_ctxt->bhi_base,
BHI_STATUS,
BHI_STATUS_MASK,
BHI_STATUS_SHIFT);
mhi_log(MHI_MSG_CRITICAL, "BHI STATUS 0x%x\n", tx_db_val);
if (BHI_STATUS_SUCCESS != tx_db_val)
mhi_log(MHI_MSG_CRITICAL,
"Incorrect BHI status: %d retry: %d\n",
tx_db_val, i);
else
break;
usleep_range(20000, 25000);
}
dma_unmap_single(&mhi_dev_ctxt->dev_info->plat_dev->dev,
bhi_ctxt->phy_image_loc,
bhi_ctxt->image_size, DMA_TO_DEVICE);
kfree(bhi_ctxt->unaligned_image_loc);
ret_val = mhi_init_state_transition(mhi_dev_ctxt,
STATE_TRANSITION_RESET);
if (MHI_STATUS_SUCCESS != ret_val) {
mhi_log(MHI_MSG_CRITICAL,
"Failed to start state change event\n");
}
return amount_copied;
bhi_copy_error:
kfree(bhi_ctxt->unaligned_image_loc);
return amount_copied;
}
