static int mhl_msc_recv_write_stat(u8 offset, u8 value)
{
if (offset >= 2)
return -EFAULT;
switch (offset) {
case 0:
/* DCAP_RDY */
/*
* Connected Device bits changed and DEVCAP READY
*/
pr_debug("MHL: value [0x%02x]\n", value);
pr_debug("MHL: offset [0x%02x]\n", offset);
pr_debug("MHL: devcap state [0x%02x]\n",
mhl_msm_state->devcap_state);
pr_debug("MHL: MHL_STATUS_DCAP_RDY [0x%02x]\n",
MHL_STATUS_DCAP_RDY);
if (((value ^ mhl_msm_state->devcap_state) &
MHL_STATUS_DCAP_RDY)) {
if (value & MHL_STATUS_DCAP_RDY) {
if (mhl_msc_read_devcap_all() == -EBUSY) {
pr_err("READ DEVCAP FAILED to send successfully\n");
break;
}
} else {
/* peer dcap turned not ready */
/*
* Clear DEVCAP READY state
*/
}
}
break;
case 1:
/* PATH_EN */
/*
* Connected Device bits changed and PATH ENABLED
*/
if ((value ^ mhl_msm_state->path_en_state)
& MHL_STATUS_PATH_ENABLED) {
if (value & MHL_STATUS_PATH_ENABLED) {
mhl_msm_state->path_en_state
|= (MHL_STATUS_PATH_ENABLED |
MHL_STATUS_CLK_MODE_NORMAL);
mhl_msc_send_write_stat(
MHL_STATUS_REG_LINK_MODE,
mhl_msm_state->path_en_state);
} else {
mhl_msm_state->path_en_state
&= ~(MHL_STATUS_PATH_ENABLED |
MHL_STATUS_CLK_MODE_NORMAL);
mhl_msc_send_write_stat(
MHL_STATUS_REG_LINK_MODE,
mhl_msm_state->path_en_state);
}
}
break;
}
mhl_msm_state->path_en_state = value;
return 0;
}
int mhl_msc_recv_write_stat(struct mhl_tx_ctrl *mhl_ctrl,
u8 offset, u8 value)
{
if (offset >= 2)
return -EFAULT;
switch (offset) {
case 0:
/*
* connected device bits
* changed and DEVCAP READY
*/
if (((value ^ mhl_ctrl->status[offset]) &
MHL_STATUS_DCAP_RDY)) {
if (value & MHL_STATUS_DCAP_RDY) {
mhl_ctrl->devcap_state = 0;
mhl_msc_read_devcap_all(mhl_ctrl);
} else {
/*
* peer dcap turned not ready
* use old devap state
*/
pr_debug("%s: DCAP RDY bit cleared\n",
__func__);
}
}
break;
case 1:
/*
* connected device bits
* changed and PATH ENABLED
* bit set
*/
if ((value ^ mhl_ctrl->status[offset])
& MHL_STATUS_PATH_ENABLED) {
if (value & MHL_STATUS_PATH_ENABLED) {
mhl_ctrl->path_en_state
|= (MHL_STATUS_PATH_ENABLED |
MHL_STATUS_CLK_MODE_NORMAL);
mhl_msc_send_write_stat(
mhl_ctrl,
MHL_STATUS_REG_LINK_MODE,
mhl_ctrl->path_en_state);
mhl_rap_send_msc_msg(
mhl_ctrl, MHL_RAP_CONTENT_ON);
} else {
mhl_ctrl->path_en_state
&= ~(MHL_STATUS_PATH_ENABLED |
MHL_STATUS_CLK_MODE_NORMAL);
mhl_msc_send_write_stat(
mhl_ctrl,
MHL_STATUS_REG_LINK_MODE,
mhl_ctrl->path_en_state);
}
}
break;
}
mhl_ctrl->status[offset] = value;
return 0;
}
static int mhl_msc_recv_write_stat(u8 offset, u8 value)
{
if (offset >= 2)
return -EFAULT;
switch (offset) {
case 0:
pr_debug("MHL: value [0x%02x]\n", value);
pr_debug("MHL: offset [0x%02x]\n", offset);
pr_debug("MHL: devcap state [0x%02x]\n",
mhl_msm_state->devcap_state);
pr_debug("MHL: MHL_STATUS_DCAP_RDY [0x%02x]\n",
MHL_STATUS_DCAP_RDY);
if (((value ^ mhl_msm_state->devcap_state) &
MHL_STATUS_DCAP_RDY)) {
if (value & MHL_STATUS_DCAP_RDY) {
if (mhl_msc_read_devcap_all() == -EBUSY) {
pr_err("READ DEVCAP FAILED to send successfully\n");
break;
}
} else {
}
}
break;
case 1:
if ((value ^ mhl_msm_state->path_en_state)
& MHL_STATUS_PATH_ENABLED) {
if (value & MHL_STATUS_PATH_ENABLED) {
mhl_msm_state->path_en_state
|= (MHL_STATUS_PATH_ENABLED |
MHL_STATUS_CLK_MODE_NORMAL);
mhl_msc_send_write_stat(
MHL_STATUS_REG_LINK_MODE,
mhl_msm_state->path_en_state);
} else {
mhl_msm_state->path_en_state
&= ~(MHL_STATUS_PATH_ENABLED |
MHL_STATUS_CLK_MODE_NORMAL);
mhl_msc_send_write_stat(
MHL_STATUS_REG_LINK_MODE,
mhl_msm_state->path_en_state);
}
}
break;
}
mhl_msm_state->path_en_state = value;
return 0;
}
static void mhl_msm_connection(struct mhl_tx_ctrl *mhl_ctrl)
{
uint8_t val;
struct i2c_client *client = mhl_ctrl->i2c_handle;
pr_debug("%s: cur st [0x%x]\n", __func__,
mhl_ctrl->cur_state);
if (mhl_ctrl->cur_state == POWER_STATE_D0_MHL) {
/* Already in D0 - MHL power state */
pr_err("%s: cur st not D0\n", __func__);
return;
}
switch_mode(mhl_ctrl, POWER_STATE_D0_MHL, true);
MHL_SII_REG_NAME_WR(REG_MHLTX_CTL1, 0x10);
MHL_SII_CBUS_WR(0x07, 0xF2);
/*
* Keep the discovery enabled. Need RGND interrupt
* Possibly chip disables discovery after MHL_EST??
* Need to re-enable here
*/
val = MHL_SII_PAGE3_RD(0x10);
MHL_SII_PAGE3_WR(0x10, val | BIT0);
/*
* indicate DCAP_RDY and DCAP_CHG
* to the peer only after
* msm conn has been established
*/
mhl_msc_send_write_stat(mhl_ctrl,
MHL_STATUS_REG_CONNECTED_RDY,
MHL_STATUS_DCAP_RDY);
mhl_msc_send_set_int(mhl_ctrl,
MHL_RCHANGE_INT,
MHL_INT_DCAP_CHG,
MSC_PRIORITY_SEND);
}
