void mipi_dsi_ahb_ctrl(u32 enable)
{
static int ahb_ctrl_done;
if (enable) {
if (ahb_ctrl_done) {
pr_info("%s: ahb clks already ON\n", __func__);
return;
}
clk_enable(amp_pclk); /* clock for AHB-master to AXI */
clk_enable(dsi_m_pclk);
clk_enable(dsi_s_pclk);
mipi_dsi_ahb_en();
mipi_dsi_sfpb_cfg();
ahb_ctrl_done = 1;
} else {
if (ahb_ctrl_done == 0) {
pr_info("%s: ahb clks already OFF\n", __func__);
return;
}
clk_disable(dsi_m_pclk);
clk_disable(dsi_s_pclk);
clk_disable(amp_pclk); /* clock for AHB-master to AXI */
ahb_ctrl_done = 0;
}
}
void mipi_dsi_ahb_ctrl(u32 enable)
{
if (enable) {
clk_enable(amp_pclk); /* clock for AHB-master to AXI */
clk_enable(dsi_m_pclk);
clk_enable(dsi_s_pclk);
mipi_dsi_ahb_en();
mipi_dsi_sfpb_cfg();
} else {
clk_disable(dsi_m_pclk);
clk_disable(dsi_s_pclk);
clk_disable(amp_pclk); /* clock for AHB-master to AXI */
}
}
void mipi_dsi_clk_enable(void)
{
if (mipi_dsi_clk_on) {
pr_err("%s: mipi_dsi_clk already ON\n", __func__);
return;
}
mipi_dsi_clk_on = 1;
clk_enable(amp_pclk); /* clock for AHB-master to AXI */
clk_enable(dsi_m_pclk);
clk_enable(dsi_s_pclk);
if (clk_set_rate(dsi_byte_div_clk, 1) < 0) /* divided by 1 */
pr_err("%s: clk_set_rate failed\n", __func__);
clk_enable(dsi_byte_div_clk);
clk_enable(dsi_esc_clk);
mipi_dsi_pclk_ctrl(&dsi_pclk, 1);
mipi_dsi_clk_ctrl(&dsicore_clk, 1);
mipi_dsi_ahb_en();
mipi_dsi_sfpb_cfg();
}
static int mipi_dsi_on(struct platform_device *pdev)
{
int ret = 0;
u32 clk_rate;
struct msm_fb_data_type *mfd;
struct fb_info *fbi;
struct fb_var_screeninfo *var;
u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height;
mfd = platform_get_drvdata(pdev);
fbi = mfd->fbi;
var = &fbi->var;
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(1);
clk_rate = mfd->fbi->var.pixclock;
clk_rate = min(clk_rate, mfd->panel_info.clk_max);
if (clk_set_rate(dsi_byte_div_clk, 1) < 0) /* divided by 1 */
printk(KERN_ERR "%s: clk_set_rate failed\n",
__func__);
clk_enable(amp_pclk);
clk_enable(dsi_m_pclk);
clk_enable(dsi_byte_div_clk);
clk_enable(dsi_esc_clk);
hbp = var->left_margin;
hfp = var->right_margin;
vbp = var->upper_margin;
vfp = var->lower_margin;
hspw = var->hsync_len;
vspw = var->vsync_len;
width = mfd->panel_info.xres;
height = mfd->panel_info.yres;
mipi_dsi_ahb_en();
mipi_dsi_sfpb_cfg();
mipi_dsi_clk(1);
mipi_dsi_pclk(1);
mipi_dsi_phy_init(0); /* toshiba video */
enable_irq(DSI_IRQ);
/*
* turn esc, byte, dsi, pclk, sclk, hclk on
*/
MIPI_OUTP(MIPI_DSI_BASE + 0x118, 0x23f); /* DSI_CLK_CTRL */
if (mfd->panel_info.type == MIPI_VIDEO_PANEL) {
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hbp + width - 1) << 16 | (hbp - 1)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vbp + height - 1) << 16 | (vbp - 1)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vbp + height + vfp - 1) << 16 |
(hbp + width + hfp - 1));
MIPI_OUTP(MIPI_DSI_BASE + 0x2c, (hspw - 1) << 16);
MIPI_OUTP(MIPI_DSI_BASE + 0x30, 0);
MIPI_OUTP(MIPI_DSI_BASE + 0x34, (vspw - 1) << 16);
/* there has hardware problem
* the color channel between dsi and mdp are swapped
*/
MIPI_OUTP(MIPI_DSI_BASE + 0x1c, 0x2000); /* rGB --> BGR */
/* embedded mode, lpm */
MIPI_OUTP(MIPI_DSI_BASE + 0x38, 0x14000000);
/* non burst sync pulse, 888RGB */
MIPI_OUTP(MIPI_DSI_BASE + 0x0c, 0x11119030);
}
MIPI_OUTP(MIPI_DSI_BASE + 0x0080, 0x04);/* sw trigger */
/* command mode */
MIPI_OUTP(MIPI_DSI_BASE + 0x0, 0x135);
wmb();
ret = panel_next_on(pdev);
/* video mode */
MIPI_OUTP(MIPI_DSI_BASE + 0x0, 0x133);
wmb();
pm_qos_update_request(mfd->pm_qos_req, 122000);
return ret;
}