Ejemplo n.º 1
0
void mipi_dsi_clk_disable(void)
{
	if (mipi_dsi_clk_on == 0) {
		pr_err("%s: mipi_dsi_clk already OFF\n", __func__);
		return;
	}

	mipi_dsi_clk_on = 0;

	MIPI_OUTP(MIPI_DSI_BASE + 0x0118, 0);

	mipi_dsi_pclk_ctrl(&dsi_pclk, 0);
	mipi_dsi_clk_ctrl(&dsicore_clk, 0);
	clk_disable(dsi_esc_clk);
	clk_disable(dsi_byte_div_clk);
	clk_disable(dsi_m_pclk);
	clk_disable(dsi_s_pclk);
	clk_disable(amp_pclk); /* clock for AHB-master to AXI */
}
Ejemplo n.º 2
0
void mipi_dsi_clk_enable(void)
{
	if (mipi_dsi_clk_on) {
		pr_err("%s: mipi_dsi_clk already ON\n", __func__);
		return;
	}

	mipi_dsi_clk_on = 1;

	clk_enable(amp_pclk); /* clock for AHB-master to AXI */
	clk_enable(dsi_m_pclk);
	clk_enable(dsi_s_pclk);
	if (clk_set_rate(dsi_byte_div_clk, 1) < 0)	/* divided by 1 */
		pr_err("%s: clk_set_rate failed\n",	__func__);
	clk_enable(dsi_byte_div_clk);
	clk_enable(dsi_esc_clk);
	mipi_dsi_pclk_ctrl(&dsi_pclk, 1);
	mipi_dsi_clk_ctrl(&dsicore_clk, 1);
	mipi_dsi_ahb_en();
	mipi_dsi_sfpb_cfg();
}
Ejemplo n.º 3
0
void mipi_dsi_clk_enable(void)
{
	u32 pll_ctrl = MIPI_INP(MIPI_DSI_BASE + 0x0200);
	if (mipi_dsi_clk_on) {
		pr_info("%s: mipi_dsi_clks already ON\n", __func__);
		return;
	}
	MIPI_OUTP(MIPI_DSI_BASE + 0x0200, pll_ctrl | 0x01);
	mipi_dsi_phy_rdy_poll();

	if (clk_set_rate(dsi_byte_div_clk, 1) < 0)	/* divided by 1 */
		pr_err("%s: dsi_byte_div_clk - "
			"clk_set_rate failed\n", __func__);
	if (clk_set_rate(dsi_esc_clk, 2) < 0) /* divided by 2 */
		pr_err("%s: dsi_esc_clk - "
			"clk_set_rate failed\n", __func__);
	mipi_dsi_pclk_ctrl(&dsi_pclk, 1);
	mipi_dsi_clk_ctrl(&dsicore_clk, 1);
	clk_enable(dsi_byte_div_clk);
	clk_enable(dsi_esc_clk);
	mipi_dsi_clk_on = 1;
	mdp4_stat.dsi_clk_on++;
}
Ejemplo n.º 4
0
void mipi_dsi_clk_disable(void)
{
	if (mipi_dsi_clk_on == 0) {
		pr_err("%s: mipi_dsi_clk already OFF\n", __func__);
		return;
	}

	mipi_dsi_clk_on = 0;

	MIPI_OUTP(MIPI_DSI_BASE + 0x0118, 0);

	mipi_dsi_pclk_ctrl(&dsi_pclk, 0);
	mipi_dsi_clk_ctrl(&dsicore_clk, 0);
	clk_disable(dsi_esc_clk);
	clk_disable(dsi_byte_div_clk);
	clk_disable(mdp_dsi_pclk);
	clk_disable(ahb_m_clk);
	clk_disable(ahb_s_clk);
	clk_disable(dsi_ref_clk);
	if (clk_set_min_rate(ebi1_dsi_clk, 0))
		pr_err("%s: ebi1_dsi_clk set rate failed\n", __func__);
	clk_disable(ebi1_dsi_clk);
}