void set4160(void)
{
mmio_write(FUC_NEWSCRATCH_SET3, 0x400);
mmwr(0x404160, 1, 0, 0);
while (!(mmrd(0x404160, 0) & 0x10));
mmio_write(FUC_NEWSCRATCH_CLEAR3, 0x400);
}
/*
* entry point into the microcontroller code.
*/
int main(void)
{
int i=0;
mmio_write(FUC_ACCESS_EN,FUC_AE_BIT_FIFO);
mmio_write(0x04,0xffffffff);//intr_line all reset
mmio_write(0x0c,0xfc04);
mmio_write(0x20,0xfffffff);// timer period
mmio_write(0x24,0xfffffff);// current timer
mmio_write(0x28,0x1); //timer enabled
//use iv0 & 1, intr_line[0]=iv0,intr_line[1]=iv1
mmio_write(FUC_INTR_DISPATCH,0x00010000); //0-15bit => 0bit 16-31bit => 1bit
mmio_write(FUC_INTR_EN_SET, 0x8705); // intrrupt_line mask set
set_flags(ie1);//ihbody1
set_flags(ie0);//ihbody
//mmio_write(0xc24, 0xffffffff);//INTR_UP_ENABLE??
set_flags($p2);
while(1){
sleep($p2);
mmio_write(0x814,j);
mmio_write(0x810,k);
}
return 0;
}
void rtc_init(int minor)
{
uint32_t a = 0x0;
rtc_clk_init();
/*
* Steps to enable RTC
* 1. Enable the module clock domains (rtc_clk_init).
* 2. Enable the RTC module using CTRL_REG.RTC_disable. (Default enabled. Nothing done)
* 3. Enable the 32K clock from PER PLL, if using the internal RTC oscillator.
* 4. Write to the kick registers (KICK0R, KICK1R) in the RTC.
* 5. Configure the timer in RTCSS for desired application (set time and date, alarm wakeup, and so on).
* 6. Start the RTC (in CTRL_REG.STOP_RTC).
*/
rtc_write_enable();
a = setbit(a,0);
mmio_write(AM335X_RTC_BASE+AM335X_RTC_SYSCONFIG,a);
a = mmio_read(AM335X_RTC_BASE+AM335X_RTC_OSC_CLOCK);
a = setbit(a,6);
mmio_write(AM335X_RTC_BASE+AM335X_RTC_OSC_CLOCK,a);
a = mmio_read(AM335X_RTC_BASE+AM335X_RTC_CTRL_REG);
a = setbit(a,0);
mmio_write(AM335X_RTC_BASE+AM335X_RTC_CTRL_REG,a);
rtc_write_disable();
}
void clear4160(void)
{
mmio_write(FUC_NEWSCRATCH_SET3, 0x800);
// waitdone_12();
mmwr(0x404160, 0, 0, 0);
mmio_write(FUC_NEWSCRATCH_CLEAR3, 0x800);
}
/*---------------------------------------------------------------------------
Writes a byte to the serial port by waiting
---------------------------------------------------------------------------*/
void uart_putc(uint32_t character)
{
if(character == '\n'){
while(!(mmio_read(AUX_MU_LSR_REG) & 0x20));
mmio_write(AUX_MU_IO_REG, '\r');
}
while(!(mmio_read(AUX_MU_LSR_REG) & 0x20));
mmio_write(AUX_MU_IO_REG, character);
} // End uart_putc()
void gpioWrite(int pinno, int level)
{
if(pinno >= 32){
pinno = pinno - 32;
mmio_write(level ? GPSET1 : GPCLR1, (1 << pinno));
}else{
mmio_write(level ? GPSET0 : GPCLR0, (1 << pinno));
}
}
void ihbody(void)
{
unsigned int intr = mmio_read(0x08);
if(intr & 0x8){
mmio_write(0x804,mmio_read(0x0804)+1);
}
j++;
mmio_write(0x74,1);
mmio_write(0x04,intr);
}
void mmwr(uint32_t addr, int val, uint32_t u1, uint32_t u2)
{
extr(addr, addr, 2, 25);
mmio_write(FUC_MMIO_WRVAL, val);
mmio_write(FUC_MMIO_CTRL, (addr << 2) |
(u1 & 1) | 0xc0000000 | (!!u2) << 29);
while (mmio_read(FUC_MMIO_CTRL) & 0x80000000);
if (u2)
while (!(mmio_read(FUC_DONE)&0x80));
}
void ihbody1(void)
{
unsigned int intr = mmio_read(0x08);
mmio_write(0x04,0x1);
// if(intr == 0x1){
mmio_write(0x800,mmio_read(0x0800)+1);
// }
k++;
// mmio_write(0x28,1);
}
/*
* Initialize RTC clock
*/
static void rtc_clk_init(void)
{
uint32_t a = 0x0;
a = setbit(a,1);
/* IDLEST = 0x0 & MODULEMODE = 0x1*/
mmio_write(CM_RTC_BASE+CM_RTC_RTC_CLKCTRL,a);
a = 0x0;
/*32K rtc clock active*/
a = setbit(a,9);
a = setbit(a,8);
mmio_write(CM_RTC_BASE+CM_RTC_CLKSTCTRL,a);
}
/*
* entry point into the micrcontroller code.
*/
int main(void)
{
int offset = 0;
int sizel2 = 4;
int local_addr = 0x400;
int xdata;
mmio_write(FUC_NEWSCRATCH_SET2,1);
mmio_write(FUC_ACCESS_EN, FUC_AE_BIT_FIFO);
mmio_write(FUC_INTR_DISPATCH, 0); // fuc interrupt 0
mmio_write(FUC_INTR_EN_SET, 0x8704);
mmio_write(0x00c, 4);
set_flags(ie0);
set_flags($p2);
int i=0;
mmio_write(0xc24, 0xffffffff);//INTR_UP_ENABLE??
while(1){
mmio_write(FUC_NEWSCRATCH4,0x87654321);
sleep($p2);
mmio_write(FUC_NEWSCRATCH5,++i);
work();
set_flags($p2);
}
return 0;
}
void uart_init() {
mmio_write(UART0_CR, 0x00000000);
mmio_write(GPPUD, 0x00000000);
delay(150);
mmio_write(GPPUDCLK0, BIT_AT(14) | BIT_AT(15));
delay(150);
mmio_write(GPPUDCLK0, 0x00000000);
mmio_write(UART0_ICR, 0x7FF);
mmio_write(UART0_IBRD, 1);
mmio_write(UART0_FBRD, 40);
mmio_write(UART0_LCRH, BIT_AT(4) | BIT_AT(5) | BIT_AT(6));
mmio_write(UART0_IMSC, BIT_AT(1) | BIT_AT(4) | BIT_AT(5) | BIT_AT(6) | BIT_AT(7) | BIT_AT(8) | BIT_AT(9) | BIT_AT(10));
mmio_write(UART0_CR, BIT_AT(0) | BIT_AT(8) | BIT_AT(9));
}
/* no '0x' prefix, NO trailing newline */
void print_word_hex(uint32_t * c){
int i;
uint32_t a;
for(i = 0x7; i >= 0x0; i--){
a = *c & (0xf << (i*0x4));
a >>= (i*0x4);
if(a <= 9)
mmio_write(UART0_ADDRESS, (uint32_t)(a + (uint32_t )'0'));
else if(a <= 0xf)
mmio_write(UART0_ADDRESS, (uint32_t)((a - 0xa) + (uint32_t )'a'));
else
mmio_write(UART0_ADDRESS, (uint32_t)('?'));
}
}
void SA1::bus_write(unsigned addr, uint8 data) {
if((addr & 0x40fe00) == 0x002200) { //$00-3f|80-bf:2200-23ff
return mmio_write(addr, data);
}
if((addr & 0x40e000) == 0x006000) { //$00-3f|80-bf:6000-7fff
return mmc_sa1_write(addr, data);
}
if((addr & 0x40f800) == 0x000000) { //$00-3f|80-bf:0000-07ff
synchronize_cpu();
return iram.write(addr & 2047, data);
}
if((addr & 0x40f800) == 0x003000) { //$00-3f|80-bf:3000-37ff
synchronize_cpu();
return iram.write(addr & 2047, data);
}
if((addr & 0xf00000) == 0x400000) { //$40-4f:0000-ffff
synchronize_cpu();
return bwram.write(addr & (bwram.size() - 1), data);
}
if((addr & 0xf00000) == 0x600000) { //$60-6f:0000-ffff
synchronize_cpu();
return bitmap_write(addr & 0x0fffff, data);
}
}
void SMP::op_write(uint16 addr, uint8 data) {
#if defined(CYCLE_ACCURATE)
tick();
#endif
if((addr & 0xfff0) == 0x00f0) mmio_write(addr, data);
apuram[addr] = data; //all writes go to RAM, even MMIO writes
}
static void
uart_putc(unsigned char byte)
{
// Wait for UART to become ready to transmit.
while ( mmio_read(UART0_FR) & (1 << 5) ) { }
mmio_write(UART0_DR, byte);
}
int mailbox_write(unsigned int value, unsigned int channel) {
printk("MAILBOX_WRITE: writing value=%x channel %x\n",
value,channel);
/* Bottom 4 bits of value must be 0 */
if (value&0xf) {
printk("mailbox_write: bottom bits not zero %x\n",
value);
return -1;
}
/* Channel must fit in 4 bits */
if (channel>15) {
printk("mailbox_write: channel too high %x\n",
channel);
return -1;
}
/* Wait until mailbox is ready */
while( (mmio_read(MAILBOX_STATUS) & MAIL_FULL) ) {
printk("Write mailbox full!\n");
}
/* write the command */
mmio_write(MAILBOX_WRITE,channel|value);
return 0;
}
void xfer(int base, int offset, int sizel2, int local_addr,
int subtrg, int trg, int dir, int wait)
{
int tspec;
mmio_write(FUC_NEWSCRATCH_SET3, 0x200);
switch (trg) {
case 2:
tspec = 1;
break;
case 1:
switch (subtrg) {
case 0:
tspec = 0x80000002;
break;
case 2:
tspec = 0x80000004;
break;
case 3:
tspec = 0x80000003;
break;
default:
tspec = 0x80000000;
break;
}
break;
default:
tspec = 0;
break;
}
mmio_write(0xa20, tspec);
set_xdbase(base);
set_xtargets(0);
mmio_write(0x10c, 0);
if (dir == 1) {
xdld(offset, (sizel2 << 0x10) | local_addr);
} else {
xdst(offset, (sizel2 << 0x10) | local_addr);
}
if (wait == 2)
xdwait();
mmio_write(0xa20, 0);
mmio_write(FUC_NEWSCRATCH_CLEAR3, 0x200);
}
void print_uart0(const char *s)
{
while (*s != '\0')
{
mmio_write(UART0_ADDRESS, *s);
s++;
}
}
void uart_putc ( unsigned int c )
{
while(1)
{
if(mmio_read(AUX_MU_LSR_REG)&0x20) break;
}
mmio_write(AUX_MU_IO_REG,c);
}
int uart_putc(int byte)
{
while(mmio_read(UART0_FR) & (1 << 5))
usleep(2000);
mmio_write(UART0_DR, (uint8_t)(byte & 0xff));
return byte;
}
void enqueue(uint32_t cmd, uint32_t data)
{
struct qe *ptr;
mmio_write(FUC_NEWSCRATCH_SET2, 2);
ptr = &queue[qput & 7];
if ((qget & 7) == (qput & 7) && (qget & 8) != (qput & 8)) {
error(0x12); // inline
} else {
ptr->data = data;
ptr->cmd = cmd;
if (++qput == 0x10)
qput = 0;
}
mmio_write(FUC_NEWSCRATCH_CLEAR2, 2);
}
void uart_putc(uint8_t byte) {
// wait for UART to become ready to transmit
while (1) {
if (!(mmio_read(UART0_FR) & (1 << 5))) {
break;
}
}
mmio_write(UART0_DR, byte);
}
int mmrd (uint32_t addr, uint32_t u1)
{
extr(addr, addr, 2, 25);
addr = addr << 2;
mmio_write(FUC_MMIO_CTRL, addr | (u1 & 1) | 0x80000000);
while (mmio_read(FUC_MMIO_CTRL) & 0x80000000);
while (!(mmio_read(FUC_DONE) & 0x40));
return mmio_read(FUC_MMIO_RDVAL);
}
void gpioSetInput(int no)
{
int pinno=no%10;
int bankno=get_fsel_bank_no(pinno);
int ireg=mmio_read(bankno);
ireg &= ~(1 << (pinno*3));
mmio_write(bankno, ireg);
}
void init_timer()
{
mmio_write(INT_IRQ_BASIC_DISABLE, 1);
mmio_write(TIMER_CONTROL, 0x3E0000);
mmio_write(TIMER_PREDIV, 0xFA);
mmio_write(TIMER_LOAD, 1000-1);
mmio_write(TIMER_RELOAD, 1000-1);
mmio_write(TIMER_IRQ_CLEAR, 0);
mmio_write(TIMER_CONTROL, 0x003E00A2);
mmio_write(INT_IRQ_BASIC_ENABLE, 1);
}
void gpioWriteSafe(int pinno, int level)
{
int regval;
if(pinno >= 32){
pinno = pinno - 32;
regval = mmio_read(GPLEV1);
}else{
regval = mmio_read(GPLEV0);
}
regval |= (1 << pinno);
if(pinno >= 32){
mmio_write(level ? GPSET1 : GPCLR1, regval);
}else{
mmio_write(level ? GPSET0 : GPCLR0, regval);
}
}
void omap3_timer_int_handler()
{
/* Clear all interrupts */
u32_t tisr;
tisr = OMAP3_TISR_MAT_IT_FLAG | OMAP3_TISR_OVF_IT_FLAG |
OMAP3_TISR_TCAR_IT_FLAG;
mmio_write(OMAP3_GPTIMER1_TISR, tisr);
tsc++;
}
void omap3_irq_handle(void) {
/* Function called from assembly to handle interrupts */
/* get irq */
int irq = mmio_read(omap_intr.base + OMAP3_INTCPS_SIR_IRQ) & OMAP3_INTR_ACTIVEIRQ_MASK;
/* handle irq */
irq_handle(irq);
/* re-enable. this should not trigger interrupts due to current cpsr state */
mmio_write(omap_intr.base + OMAP3_INTCPS_CONTROL,OMAP3_INTR_NEWIRQAGR);
}
static void
uart_init(void)
{
// Disable UART0.
mmio_write(UART0_CR, 0x00000000);
// Setup the GPIO pin 14 && 15.
// Disable pull up/down for all GPIO pins & delay for 150 cycles.
mmio_write(GPPUD, 0x00000000);
delay(150);
// Disable pull up/down for pin 14,15 & delay for 150 cycles.
mmio_write(GPPUDCLK0, (1 << 14) | (1 << 15));
delay(150);
// Write 0 to GPPUDCLK0 to make it take effect.
mmio_write(GPPUDCLK0, 0x00000000);
// Clear pending interrupts.
mmio_write(UART0_ICR, 0x7FF);
// Set integer & fractional part of baud rate.
// Divider = UART_CLOCK/(16 * Baud)
// Fraction part register = (Fractional part * 64) + 0.5
// UART_CLOCK = 3000000; Baud = 115200.
// Divider = 3000000 / (16 * 115200) = 1.627 = ~1.
// Fractional part register = (.627 * 64) + 0.5 = 40.6 = ~40.
mmio_write(UART0_IBRD, 1);
mmio_write(UART0_FBRD, 40);
// Enable FIFO & 8 bit data transmissio (1 stop bit, no parity).
mmio_write(UART0_LCRH, (1 << 4) | (1 << 5) | (1 << 6));
// Mask all interrupts.
mmio_write(UART0_IMSC, (1 << 1) | (1 << 4) | (1 << 5) | (1 << 6) |
(1 << 7) | (1 << 8) | (1 << 9) | (1 << 10));
// Enable UART0, receive & transfer part of UART.
mmio_write(UART0_CR, (1 << 0) | (1 << 8) | (1 << 9));
}
