void bfa_hwcb_rspq_ack(struct bfa_s *bfa, int rspq, u32 ci) { if (bfa_rspq_ci(bfa, rspq) == ci) return; bfa_rspq_ci(bfa, rspq) = ci; writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]); mmiowb(); }
static inline u16 qed_attn_update_idx(struct qed_hwfn *p_hwfn, struct qed_sb_attn_info *p_sb_desc) { u16 rc = 0; u16 index; /* Make certain HW write took affect */ mmiowb(); index = le16_to_cpu(p_sb_desc->sb_attn->sb_index); if (p_sb_desc->index != index) { p_sb_desc->index = index; rc = QED_SB_ATT_IDX; } /* Make certain we got a consistent view with HW */ mmiowb(); return rc; }
static int txx9_gpio_dir_out(struct gpio_chip *chip, unsigned int offset, int value) { spin_lock_irq(&txx9_gpio_lock); txx9_gpio_set_raw(offset, value); __raw_writel(__raw_readl(&txx9_pioptr->dir) | (1 << offset), &txx9_pioptr->dir); mmiowb(); spin_unlock_irq(&txx9_gpio_lock); return 0; }
static void fl2f_shutdown(void) { u32 hi, lo, val; int gpio_base; /* get gpio base */ _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_GPIO), &hi, &lo); gpio_base = lo & 0xff00; /* make cs5536 gpio13 output enable */ val = inl(gpio_base + GPIOL_OUT_EN); val &= ~(1 << (16 + 13)); val |= (1 << 13); outl(val, gpio_base + GPIOL_OUT_EN); mmiowb(); /* make cs5536 gpio13 output low level voltage. */ val = inl(gpio_base + GPIOL_OUT_VAL) & ~(1 << (13)); val |= (1 << (16 + 13)); outl(val, gpio_base + GPIOL_OUT_VAL); mmiowb(); }
/* * Actions to respond RME Interrupt for Catapult ASIC: * - Write 1 to Interrupt Status register (INTx only - done in bfa_intx()) * - Acknowledge by writing to RME Queue Control register * - Update CI */ void bfa_hwct_rspq_ack(struct bfa_s *bfa, int rspq, u32 ci) { u32 r32; r32 = readl(bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]); writel(r32, bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]); bfa_rspq_ci(bfa, rspq) = ci; writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]); mmiowb(); }
static inline void ring_doorbell(struct octeon_device *oct, struct octeon_instr_queue *iq) { if (atomic_read(&oct->status) == OCT_DEV_RUNNING) { writel(iq->fill_cnt, iq->doorbell_reg); /* make sure doorbell write goes through */ mmiowb(); iq->fill_cnt = 0; iq->last_db_time = jiffies; return; } }
static void cpt_write_infoframe(struct drm_encoder *encoder, struct dip_infoframe *frame) { uint32_t *data = (uint32_t *)frame; struct drm_device *dev = encoder->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); unsigned i, len = DIP_HEADER_SIZE + frame->len; u32 val = I915_READ(reg); WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val |= g4x_infoframe_index(frame); /* The DIP control register spec says that we need to update the AVI * infoframe without clearing its enable bit */ if (frame->type != DIP_TYPE_AVI) val &= ~g4x_infoframe_enable(frame); I915_WRITE(reg, val); mmiowb(); for (i = 0; i < len; i += 4) { I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); data++; } /* Write every possible data byte to force correct ECC calculation. */ for (; i < VIDEO_DIP_DATA_SIZE; i += 4) I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); mmiowb(); val |= g4x_infoframe_enable(frame); val &= ~VIDEO_DIP_FREQ_MASK; val |= VIDEO_DIP_FREQ_VSYNC; I915_WRITE(reg, val); POSTING_READ(reg); }
static u16 w5300_read_indirect(struct w5300_priv *priv, u16 addr) { unsigned long flags; u16 data; spin_lock_irqsave(&priv->reg_lock, flags); w5300_write_direct(priv, W5300_IDM_AR, addr); mmiowb(); data = w5300_read_direct(priv, W5300_IDM_DR); spin_unlock_irqrestore(&priv->reg_lock, flags); return data; }
static void sc92031_enable_interrupts(struct net_device *dev) { struct sc92031_priv *priv = netdev_priv(dev); void __iomem *port_base = priv->port_base; tasklet_enable(&priv->tasklet); atomic_set(&priv->intr_mask, IntrBits); wmb(); iowrite32(IntrBits, port_base + IntrMask); mmiowb(); }
/* * Actions to respond RME Interrupt for Crossbow ASIC: * - Write 1 to Interrupt Status register * INTX - done in bfa_intx() * MSIX - done in bfa_hwcb_rspq_ack_msix() * - Update CI (only if new CI) */ static void bfa_hwcb_rspq_ack_msix(struct bfa_s *bfa, int rspq, u32 ci) { writel(__HFN_INT_RME_Q0 << RME_Q_NUM(bfa_ioc_pcifn(&bfa->ioc), rspq), bfa->iocfc.bfa_regs.intr_status); if (bfa_rspq_ci(bfa, rspq) == ci) return; bfa_rspq_ci(bfa, rspq) = ci; writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]); mmiowb(); }
static void tx4938_write_buffer_flush(void) { mmiowb(); __asm__ __volatile__(".set push\n\t" ".set noreorder\n\t" "lw $0,%0\n\t" "nop\n\t" ".set pop" : /* no output */ :"m"(*(int *)KSEG1) :"memory"); }
void iwl_release_nic_access(struct iwl_trans *trans) { lockdep_assert_held(&trans->reg_lock); __iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); /* * Above we read the CSR_GP_CNTRL register, which will flush * any previous writes, but we need the write that clears the * MAC_ACCESS_REQ bit to be performed before any other writes * scheduled on different CPUs (after we drop reg_lock). */ mmiowb(); }
static void vlv_write_infoframe(struct drm_encoder *encoder, struct dip_infoframe *frame) { uint32_t *data = (uint32_t *)frame; struct drm_device *dev = encoder->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); unsigned i, len = DIP_HEADER_SIZE + frame->len; u32 val = I915_READ(reg); intel_wait_for_vblank(dev, intel_crtc->pipe); val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val |= g4x_infoframe_index(frame); val &= ~g4x_infoframe_enable(frame); val |= VIDEO_DIP_ENABLE; I915_WRITE(reg, val); mmiowb(); for (i = 0; i < len; i += 4) { I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); data++; } /* Write every possible data byte to force correct ECC calculation. */ for (; i < VIDEO_DIP_DATA_SIZE; i += 4) I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); mmiowb(); val |= g4x_infoframe_enable(frame); val &= ~VIDEO_DIP_FREQ_MASK; val |= VIDEO_DIP_FREQ_VSYNC; I915_WRITE(reg, val); POSTING_READ(reg); }
static void tx4938_irq_pic_modify(unsigned pic_reg, unsigned clr_bits, unsigned set_bits) { unsigned long val = 0; val = TX4938_RD(pic_reg); val &= (~clr_bits); val |= (set_bits); TX4938_WR(pic_reg, val); mmiowb(); TX4938_RD(pic_reg); return; }
static void vlv_write_infoframe(struct drm_encoder *encoder, enum hdmi_infoframe_type type, const void *frame, ssize_t len) { const uint32_t *data = frame; struct drm_device *dev = encoder->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); u32 val = I915_READ(reg); WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val |= g4x_infoframe_index(type); val &= ~g4x_infoframe_enable(type); I915_WRITE(reg, val); mmiowb(); for (i = 0; i < len; i += 4) { I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); data++; } /* Write every possible data byte to force correct ECC calculation. */ for (; i < VIDEO_DIP_DATA_SIZE; i += 4) I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); mmiowb(); val |= g4x_infoframe_enable(type); val &= ~VIDEO_DIP_FREQ_MASK; val |= VIDEO_DIP_FREQ_VSYNC; I915_WRITE(reg, val); POSTING_READ(reg); }
static int tegra_sdhci_resume(struct platform_device *pdev) { struct tegra_sdhci_host *host = platform_get_drvdata(pdev); int ret; #ifdef CONFIG_MACH_SAMSUNG_VARIATION_TEGRA int i, present; #endif u8 pwr; if (host->card_always_on && is_card_sdio(host->sdhci->mmc->card)) { int ret = 0; if (device_may_wakeup(&pdev->dev)) { disable_irq_wake(host->sdhci->irq); } /* soft reset SD host controller and enable interrupts */ ret = tegra_sdhci_restore(host->sdhci); if (ret) { pr_err("%s: failed, error = %d\n", __func__, ret); return ret; } mmiowb(); #ifdef CONFIG_MACH_SAMSUNG_VARIATION_TEGRA for(i=0;i<20;i++){ present = sdhci_readl(host->sdhci, SDHCI_PRESENT_STATE); if((present & SDHCI_CARD_PRESENT) == SDHCI_CARD_PRESENT) break; mdelay(5); // printk(KERN_ERR "MMC : %s : 6(Card Presnet %x) : %d \n",mmc_hostname(host->sdhci->mmc),present,i); } #endif host->sdhci->mmc->ops->set_ios(host->sdhci->mmc, &host->sdhci->mmc->ios); return 0; } tegra_sdhci_enable_clock(host, 1); pwr = SDHCI_POWER_ON; sdhci_writeb(host->sdhci, pwr, SDHCI_POWER_CONTROL); host->sdhci->pwr = 0; ret = sdhci_resume_host(host->sdhci); if (ret) pr_err("%s: failed, error = %d\n", __func__, ret); return ret; }
void mite_dma_arm(struct mite_channel *mite_chan) { struct mite_struct *mite = mite_chan->mite; int chor; unsigned long flags; MDPRINTK("mite_dma_arm ch%i\n", channel); smp_mb(); chor = CHOR_START; spin_lock_irqsave(&mite->lock, flags); mite_chan->done = 0; writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); mmiowb(); spin_unlock_irqrestore(&mite->lock, flags); }
static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq) { unsigned long flags; volatile unsigned char v; spin_lock_irqsave(&toshiba_rbtx4938_ioc_lock, flags); v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v); mmiowb(); TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); spin_unlock_irqrestore(&toshiba_rbtx4938_ioc_lock, flags); }
/** * write_i2c_reg - writes to an internal i2c register * * @addr: dt3155 mmio base address * @index: index (internal address) of register to read * @data: data to be written * * returns: zero on success or error code * * This function starts writing the specified (by index) register * and busy waits for the process to finish. */ static int write_i2c_reg(void __iomem *addr, u8 index, u8 data) { u32 tmp = index; iowrite32((tmp << 17) | IIC_WRITE | data, addr + IIC_CSR2); mmiowb(); udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */ if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) return -EIO; /* error: NEW_CYCLE not cleared */ if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) { /* reset DIRECT_ABORT bit */ iowrite32(DIRECT_ABORT, addr + IIC_CSR1); return -EIO; /* error: DIRECT_ABORT set */ } return 0; }
static void bcm2835_sdhost_tasklet_finish(unsigned long param) { struct bcm2835_host *host; unsigned long flags; struct mmc_request *mrq; host = (struct bcm2835_host *)param; spin_lock_irqsave(&host->lock, flags); /* * If this tasklet gets rescheduled while running, it will * be run again afterwards but without any active request. */ if (!host->mrq) { spin_unlock_irqrestore(&host->lock, flags); return; } del_timer(&host->timer); mrq = host->mrq; /* Drop the overclock after any data corruption, or after any error overclocked */ if (host->overclock) { if ((mrq->cmd && mrq->cmd->error) || (mrq->data && mrq->data->error) || (mrq->stop && mrq->stop->error)) { host->overclock_50--; pr_warn("%s: reducing overclock due to errors\n", mmc_hostname(host->mmc)); bcm2835_sdhost_set_clock(host,50*MHZ); mrq->cmd->error = -EILSEQ; mrq->cmd->retries = 1; } } host->mrq = NULL; host->cmd = NULL; host->data = NULL; mmiowb(); spin_unlock_irqrestore(&host->lock, flags); mmc_request_done(host->mmc, mrq); }
unsigned mite_get_status(struct mite_channel *mite_chan) { struct mite_struct *mite = mite_chan->mite; unsigned status; unsigned long flags; comedi_spin_lock_irqsave(&mite->lock, flags); status = readl(mite->mite_io_addr + MITE_CHSR(mite_chan->channel)); if (status & CHSR_DONE) { mite_chan->done = 1; writel(CHOR_CLRDONE, mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); } mmiowb(); comedi_spin_unlock_irqrestore(&mite->lock, flags); return status; }
static void ni_pcidio_release_di_mite_channel(struct comedi_device *dev) { unsigned long flags; spin_lock_irqsave(&devpriv->mite_channel_lock, flags); if (devpriv->di_mite_chan) { mite_dma_disarm(devpriv->di_mite_chan); mite_dma_reset(devpriv->di_mite_chan); mite_release_channel(devpriv->di_mite_chan); devpriv->di_mite_chan = NULL; writeb(primary_DMAChannel_bits(0) | secondary_DMAChannel_bits(0), devpriv->mite->daq_io_addr + DMA_Line_Control_Group1); mmiowb(); } spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); }
static ssize_t b43_attr_interfmode_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { struct b43_wldev *wldev = dev_to_b43_wldev(dev); int err; int mode; if (!capable(CAP_NET_ADMIN)) return -EPERM; mode = get_integer(buf, count); switch (mode) { case 0: mode = B43_INTERFMODE_NONE; break; case 1: mode = B43_INTERFMODE_NONWLAN; break; case 2: mode = B43_INTERFMODE_MANUALWLAN; break; case 3: mode = B43_INTERFMODE_AUTOWLAN; break; default: return -EINVAL; } mutex_lock(&wldev->wl->mutex); if (wldev->phy.ops->interf_mitigation) { err = wldev->phy.ops->interf_mitigation(wldev, mode); if (err) { b43err(wldev->wl, "Interference Mitigation not " "supported by device\n"); } } else err = -ENOSYS; mmiowb(); mutex_unlock(&wldev->wl->mutex); return err ? err : count; }
static int sprom_do_write(struct ssb_bus *bus, const u16 *sprom) { struct pci_dev *pdev = bus->host_pci; int i, err; u32 spromctl; ssb_printk(KERN_NOTICE PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n"); err = pci_read_config_dword(pdev, SSB_SPROMCTL, &spromctl); if (err) goto err_ctlreg; spromctl |= SSB_SPROMCTL_WE; err = pci_write_config_dword(pdev, SSB_SPROMCTL, spromctl); if (err) goto err_ctlreg; ssb_printk(KERN_NOTICE PFX "[ 0%%"); msleep(500); for (i = 0; i < SSB_SPROMSIZE_WORDS; i++) { if (i == SSB_SPROMSIZE_WORDS / 4) ssb_printk("25%%"); else if (i == SSB_SPROMSIZE_WORDS / 2) ssb_printk("50%%"); else if (i == (SSB_SPROMSIZE_WORDS / 4) * 3) ssb_printk("75%%"); else if (i % 2) ssb_printk("."); writew(sprom[i], bus->mmio + SSB_SPROM_BASE + (i * 2)); mmiowb(); msleep(20); } err = pci_read_config_dword(pdev, SSB_SPROMCTL, &spromctl); if (err) goto err_ctlreg; spromctl &= ~SSB_SPROMCTL_WE; err = pci_write_config_dword(pdev, SSB_SPROMCTL, spromctl); if (err) goto err_ctlreg; msleep(500); ssb_printk("100%% ]\n"); ssb_printk(KERN_NOTICE PFX "SPROM written.\n"); return 0; err_ctlreg: ssb_printk(KERN_ERR PFX "Could not access SPROM control register.\n"); return err; }
/** * read_i2c_reg - reads an internal i2c register * * @addr: dt3155 mmio base address * @index: index (internal address) of register to read * @data: pointer to byte the read data will be placed in * * returns: zero on success or error code * * This function starts reading the specified (by index) register * and busy waits for the process to finish. The result is placed * in a byte pointed by data. */ static int read_i2c_reg(void __iomem *addr, u8 index, u8 *data) { u32 tmp = index; iowrite32((tmp << 17) | IIC_READ, addr + IIC_CSR2); mmiowb(); udelay(45); /* wait at least 43 usec for NEW_CYCLE to clear */ if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) return -EIO; /* error: NEW_CYCLE not cleared */ tmp = ioread32(addr + IIC_CSR1); if (tmp & DIRECT_ABORT) { /* reset DIRECT_ABORT bit */ iowrite32(DIRECT_ABORT, addr + IIC_CSR1); return -EIO; /* error: DIRECT_ABORT set */ } *data = tmp >> 24; return 0; }
static void sc92031_disable_interrupts(struct net_device *dev) { struct sc92031_priv *priv = netdev_priv(dev); void __iomem *port_base = priv->port_base; /* tell the tasklet/interrupt not to enable interrupts */ atomic_set(&priv->intr_mask, 0); wmb(); /* stop interrupts */ iowrite32(0, port_base + IntrMask); _sc92031_dummy_read(port_base); mmiowb(); /* wait for any concurrent interrupt/tasklet to finish */ synchronize_irq(dev->irq); tasklet_disable(&priv->tasklet); }
static ssize_t bcm43xx_attr_interfmode_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { struct bcm43xx_wldev *wldev = dev_to_bcm43xx_wldev(dev); unsigned long flags; int err; int mode; if (!capable(CAP_NET_ADMIN)) return -EPERM; mode = get_integer(buf, count); switch (mode) { case 0: mode = BCM43xx_INTERFMODE_NONE; break; case 1: mode = BCM43xx_INTERFMODE_NONWLAN; break; case 2: mode = BCM43xx_INTERFMODE_MANUALWLAN; break; case 3: mode = BCM43xx_INTERFMODE_AUTOWLAN; break; default: return -EINVAL; } mutex_lock(&wldev->wl->mutex); spin_lock_irqsave(&wldev->wl->irq_lock, flags); err = bcm43xx_radio_set_interference_mitigation(wldev, mode); if (err) { printk(KERN_ERR PFX "Interference Mitigation not " "supported by device\n"); } mmiowb(); spin_unlock_irqrestore(&wldev->wl->irq_lock, flags); mutex_unlock(&wldev->wl->mutex); return err ? err : count; }
void bfa_msix_rspq(struct bfa_s *bfa, int qid) { struct bfi_msg_s *m; u32 pi, ci; struct list_head *waitq; bfa_trc_fp(bfa, qid); qid &= (BFI_IOC_MAX_CQS - 1); bfa->iocfc.hwif.hw_rspq_ack(bfa, qid); ci = bfa_rspq_ci(bfa, qid); pi = bfa_rspq_pi(bfa, qid); bfa_trc_fp(bfa, ci); bfa_trc_fp(bfa, pi); if (bfa->rme_process) { while (ci != pi) { m = bfa_rspq_elem(bfa, qid, ci); bfa_assert_fp(m->mhdr.msg_class < BFI_MC_MAX); bfa_isrs[m->mhdr.msg_class] (bfa, m); CQ_INCR(ci, bfa->iocfc.cfg.drvcfg.num_rspq_elems); } } /** * update CI */ bfa_rspq_ci(bfa, qid) = pi; bfa_reg_write(bfa->iocfc.bfa_regs.rme_q_ci[qid], pi); mmiowb(); /** * Resume any pending requests in the corresponding reqq. */ waitq = bfa_reqq(bfa, qid); if (!list_empty(waitq)) bfa_reqq_resume(bfa, qid); }
void mite_dma_arm(struct mite_channel *mite_chan) { struct mite_struct *mite = mite_chan->mite; int chor; unsigned long flags; MDPRINTK("mite_dma_arm ch%i\n", channel); /* memory barrier is intended to insure any twiddling with the buffer is done before writing to the mite to arm dma transfer */ smp_mb(); /* arm */ chor = CHOR_START; comedi_spin_lock_irqsave(&mite->lock, flags); mite_chan->done = 0; writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); mmiowb(); comedi_spin_unlock_irqrestore(&mite->lock, flags); // mite_dma_tcr(mite, channel); }
static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq) { volatile unsigned char v; TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_DISABLE, "irq=%d\n", irq); if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) { TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR, "bad irq=%d\n", irq); panic("\n"); } v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); mmiowb(); }