static int
mt76_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
struct ieee80211_sta *sta)
{
struct mt76_dev *dev = hw->priv;
struct mt76_sta *msta = (struct mt76_sta *) sta->drv_priv;
struct mt76_vif *mvif = (struct mt76_vif *) vif->drv_priv;
int ret = 0;
int idx = 0;
int i;
mutex_lock(&dev->mutex);
idx = mt76_wcid_alloc(dev);
if (idx < 0) {
ret = -ENOSPC;
goto out;
}
msta->wcid.idx = idx;
msta->wcid.hw_key_idx = -1;
mt76_mac_wcid_setup(dev, idx, mvif->idx, sta->addr);
mt76_clear(dev, MT_WCID_DROP(idx), MT_WCID_DROP_MASK(idx));
for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
mt76_txq_init(dev, sta->txq[i]);
rcu_assign_pointer(dev->wcid[idx], &msta->wcid);
out:
mutex_unlock(&dev->mutex);
return ret;
}
static int
mt76_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
struct ieee80211_sta *sta)
{
struct mt76_dev *dev = hw->priv;
struct mt76_sta *msta = (struct mt76_sta *) sta->drv_priv;
int idx = msta->wcid.idx;
int i;
mutex_lock(&dev->mutex);
rcu_assign_pointer(dev->wcid[idx], NULL);
for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
mt76_txq_remove(dev, sta->txq[i]);
mt76_set(dev, MT_WCID_DROP(idx), MT_WCID_DROP_MASK(idx));
dev->wcid_mask[idx / BITS_PER_LONG] &= ~BIT(idx % BITS_PER_LONG);
mt76_mac_wcid_setup(dev, idx, 0, NULL);
mutex_unlock(&dev->mutex);
return 0;
}
int mt76_mac_reset(struct mt76_dev *dev, bool hard)
{
static const u8 null_addr[ETH_ALEN] = {};
u32 val;
int i, k;
if (!mt76_wait_for_mac(dev))
return -ETIMEDOUT;
val = mt76_rr(dev, MT_WPDMA_GLO_CFG);
val &= ~(MT_WPDMA_GLO_CFG_TX_DMA_EN |
MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
MT_WPDMA_GLO_CFG_RX_DMA_EN |
MT_WPDMA_GLO_CFG_RX_DMA_BUSY |
MT_WPDMA_GLO_CFG_DMA_BURST_SIZE);
val |= MT76_SET(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3);
mt76_wr(dev, MT_WPDMA_GLO_CFG, val);
mt76_mac_pbf_init(dev);
mt76_write_mac_initvals(dev);
mt76_fixup_xtal(dev);
mt76_clear(dev, MT_MAC_SYS_CTRL,
MT_MAC_SYS_CTRL_RESET_CSR |
MT_MAC_SYS_CTRL_RESET_BBP);
if (is_mt7612(dev))
mt76_clear(dev, MT_COEXCFG0, MT_COEXCFG0_COEX_EN);
mt76_set(dev, MT_EXT_CCA_CFG, 0x0000f000);
mt76_clear(dev, MT_TX_ALC_CFG_4, BIT(31));
mt76_wr(dev, MT_RF_BYPASS_0, 0x06000000);
mt76_wr(dev, MT_RF_SETTING_0, 0x08800000);
msleep(5);
mt76_wr(dev, MT_RF_BYPASS_0, 0x00000000);
mt76_wr(dev, MT_MCU_CLOCK_CTL, 0x1401);
mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN);
mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(dev->macaddr));
mt76_wr(dev, MT_MAC_ADDR_DW1, get_unaligned_le16(dev->macaddr + 4));
mt76_wr(dev, MT_MAC_BSSID_DW0, get_unaligned_le32(dev->macaddr));
mt76_wr(dev, MT_MAC_BSSID_DW1, get_unaligned_le16(dev->macaddr + 4) |
MT76_SET(MT_MAC_BSSID_DW1_MBSS_MODE, 3) | /* 8 beacons */
MT_MAC_BSSID_DW1_MBSS_LOCAL_BIT);
/* Fire a pre-TBTT interrupt 8 ms before TBTT */
mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_PRE_TBTT,
8 << 4);
mt76_wr(dev, MT_INT_TIMER_EN, 0);
mt76_wr(dev, MT_BCN_BYPASS_MASK, 0xffff);
if (!hard)
return 0;
for (i = 0; i < 256; i++)
mt76_mac_wcid_setup(dev, i, 0, NULL);
for (i = 0; i < 16; i++)
for (k = 0; k < 4; k++)
mt76_mac_shared_key_setup(dev, i, k, NULL);
for (i = 0; i < 8; i++) {
mt76_mac_set_bssid(dev, i, null_addr);
mt76_mac_set_beacon(dev, i, NULL);
}
for (i = 0; i < 16; i++)
mt76_rr(dev, MT_TX_STAT_FIFO);
mt76_set(dev, MT_MAC_APC_BSSID_H(0), MT_MAC_APC_BSSID0_H_EN);
mt76_init_beacon_offsets(dev);
return 0;
}
