void mt76x2_mac_set_tx_protection(struct mt76x2_dev *dev, u32 val) { u32 data = 0; if (val != ~0) data = FIELD_PREP(MT_PROT_CFG_CTRL, 1) | MT_PROT_CFG_RTS_THRESH; mt76_rmw_field(dev, MT_TX_RTS_CFG, MT_TX_RTS_CFG_THRESH, val); mt76_rmw(dev, MT_CCK_PROT_CFG, MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data); mt76_rmw(dev, MT_OFDM_PROT_CFG, MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data); mt76_rmw(dev, MT_MM20_PROT_CFG, MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data); mt76_rmw(dev, MT_MM40_PROT_CFG, MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data); mt76_rmw(dev, MT_GF20_PROT_CFG, MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data); mt76_rmw(dev, MT_GF40_PROT_CFG, MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data); mt76_rmw(dev, MT_TX_PROT_CFG6, MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data); mt76_rmw(dev, MT_TX_PROT_CFG7, MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data); mt76_rmw(dev, MT_TX_PROT_CFG8, MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data); }
void mt76x2_mac_set_beacon_enable(struct mt76x2_dev *dev, u8 vif_idx, bool val) { u8 old_mask = dev->beacon_mask; bool en; u32 reg; if (val) { dev->beacon_mask |= BIT(vif_idx); } else { dev->beacon_mask &= ~BIT(vif_idx); mt76x2_mac_set_beacon(dev, vif_idx, NULL); } if (!!old_mask == !!dev->beacon_mask) return; en = dev->beacon_mask; mt76_rmw_field(dev, MT_INT_TIMER_EN, MT_INT_TIMER_EN_PRE_TBTT_EN, en); reg = MT_BEACON_TIME_CFG_BEACON_TX | MT_BEACON_TIME_CFG_TBTT_EN | MT_BEACON_TIME_CFG_TIMER_EN; mt76_rmw(dev, MT_BEACON_TIME_CFG, reg, reg * en); if (en) mt76x2_irq_enable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT); else mt76x2_irq_disable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT); }
int mt76x2_phy_set_channel(struct mt76x02_dev *dev, struct cfg80211_chan_def *chandef) { struct ieee80211_channel *chan = chandef->chan; bool scan = test_bit(MT76_SCANNING, &dev->mt76.state); enum nl80211_band band = chan->band; u8 channel; u32 ext_cca_chan[4] = { [0] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 0) | FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 1) | FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) | FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) | FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(0)), [1] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 1) | FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 0) | FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) | FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) | FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(1)), [2] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 2) | FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 3) | FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 1) | FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 0) | FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(2)), [3] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 3) | FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 2) | FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 1) | FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 0) | FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(3)), }; int ch_group_index; u8 bw, bw_index; int freq, freq1; int ret; dev->cal.channel_cal_done = false; freq = chandef->chan->center_freq; freq1 = chandef->center_freq1; channel = chan->hw_value; switch (chandef->width) { case NL80211_CHAN_WIDTH_40: bw = 1; if (freq1 > freq) { bw_index = 1; ch_group_index = 0; } else { bw_index = 3; ch_group_index = 1; } channel += 2 - ch_group_index * 4; break; case NL80211_CHAN_WIDTH_80: ch_group_index = (freq - freq1 + 30) / 20; if (WARN_ON(ch_group_index < 0 || ch_group_index > 3)) ch_group_index = 0; bw = 2; bw_index = ch_group_index; channel += 6 - ch_group_index * 4; break; default: bw = 0; bw_index = 0; ch_group_index = 0; break; } mt76x2_read_rx_gain(dev); mt76x2_phy_set_txpower_regs(dev, band); mt76x2_configure_tx_delay(dev, band, bw); mt76x2_phy_set_txpower(dev); mt76x02_phy_set_band(dev, chan->band, ch_group_index & 1); mt76x02_phy_set_bw(dev, chandef->width, ch_group_index); mt76_rmw(dev, MT_EXT_CCA_CFG, (MT_EXT_CCA_CFG_CCA0 | MT_EXT_CCA_CFG_CCA1 | MT_EXT_CCA_CFG_CCA2 | MT_EXT_CCA_CFG_CCA3 | MT_EXT_CCA_CFG_CCA_MASK), ext_cca_chan[ch_group_index]); ret = mt76x2_mcu_set_channel(dev, channel, bw, bw_index, scan); if (ret) return ret; mt76x2_mcu_init_gain(dev, channel, dev->cal.rx.mcu_gain, true); mt76x2_phy_set_antenna(dev); /* Enable LDPC Rx */ if (mt76xx_rev(dev) >= MT76XX_REV_E3) mt76_set(dev, MT_BBP(RXO, 13), BIT(10)); if (!dev->cal.init_cal_done) { u8 val = mt76x02_eeprom_get(dev, MT_EE_BT_RCAL_RESULT); if (val != 0xff) mt76x02_mcu_calibrate(dev, MCU_CAL_R, 0); } mt76x02_mcu_calibrate(dev, MCU_CAL_RXDCOC, channel); /* Rx LPF calibration */ if (!dev->cal.init_cal_done) mt76x02_mcu_calibrate(dev, MCU_CAL_RC, 0); dev->cal.init_cal_done = true; mt76_wr(dev, MT_BBP(AGC, 61), 0xFF64A4E2); mt76_wr(dev, MT_BBP(AGC, 7), 0x08081010); mt76_wr(dev, MT_BBP(AGC, 11), 0x00000404); mt76_wr(dev, MT_BBP(AGC, 2), 0x00007070); mt76_wr(dev, MT_TXOP_CTRL_CFG, 0x04101B3F); if (scan) return 0; mt76x2_phy_channel_calibrate(dev, true); mt76x02_init_agc_gain(dev); /* init default values for temp compensation */ if (mt76x2_tssi_enabled(dev)) { mt76_rmw_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP, 0x38); mt76_rmw_field(dev, MT_TX_ALC_CFG_2, MT_TX_ALC_CFG_2_TEMP_COMP, 0x38); } ieee80211_queue_delayed_work(mt76_hw(dev), &dev->cal_work, MT_CALIBRATE_INTERVAL); return 0; } static void mt76x2_phy_temp_compensate(struct mt76x02_dev *dev) { struct mt76x2_temp_comp t; int temp, db_diff; if (mt76x2_get_temp_comp(dev, &t)) return; temp = mt76_get_field(dev, MT_TEMP_SENSOR, MT_TEMP_SENSOR_VAL); temp -= t.temp_25_ref; temp = (temp * 1789) / 1000 + 25; dev->cal.temp = temp; if (temp > 25) db_diff = (temp - 25) / t.high_slope; else db_diff = (25 - temp) / t.low_slope; db_diff = min(db_diff, t.upper_bound); db_diff = max(db_diff, t.lower_bound); mt76_rmw_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP, db_diff * 2); mt76_rmw_field(dev, MT_TX_ALC_CFG_2, MT_TX_ALC_CFG_2_TEMP_COMP, db_diff * 2); } void mt76x2_phy_calibrate(struct work_struct *work) { struct mt76x02_dev *dev; dev = container_of(work, struct mt76x02_dev, cal_work.work); mt76x2_phy_channel_calibrate(dev, false); mt76x2_phy_tssi_compensate(dev); mt76x2_phy_temp_compensate(dev); mt76x2_phy_update_channel_gain(dev); ieee80211_queue_delayed_work(mt76_hw(dev), &dev->cal_work, MT_CALIBRATE_INTERVAL); } int mt76x2_phy_start(struct mt76x02_dev *dev) { int ret; ret = mt76x02_mcu_set_radio_state(dev, true); if (ret) return ret; mt76x2_mcu_load_cr(dev, MT_RF_BBP_CR, 0, 0); return ret; }
static int mt7603_mcu_init_download(struct mt7603_dev *dev, u32 addr, u32 len) { struct { __le32 addr; __le32 len; __le32 mode; } req = { .addr = cpu_to_le32(addr), .len = cpu_to_le32(len), .mode = cpu_to_le32(BIT(31)), }; struct sk_buff *skb = mt7603_mcu_msg_alloc(&req, sizeof(req)); return mt7603_mcu_msg_send(dev, skb, -MCU_CMD_TARGET_ADDRESS_LEN_REQ, MCU_Q_NA); } static int mt7603_mcu_send_firmware(struct mt7603_dev *dev, const void *data, int len) { struct sk_buff *skb; int ret = 0; while (len > 0) { int cur_len = min_t(int, 4096 - sizeof(struct mt7603_mcu_txd), len); skb = mt7603_mcu_msg_alloc(data, cur_len); if (!skb) return -ENOMEM; ret = __mt7603_mcu_msg_send(dev, skb, -MCU_CMD_FW_SCATTER, MCU_Q_NA, NULL); if (ret) break; data += cur_len; len -= cur_len; } return ret; } static int mt7603_mcu_start_firmware(struct mt7603_dev *dev, u32 addr) { struct { __le32 override; __le32 addr; } req = { .override = cpu_to_le32(addr ? 1 : 0), .addr = cpu_to_le32(addr), }; struct sk_buff *skb = mt7603_mcu_msg_alloc(&req, sizeof(req)); return mt7603_mcu_msg_send(dev, skb, -MCU_CMD_FW_START_REQ, MCU_Q_NA); } static int mt7603_mcu_restart(struct mt7603_dev *dev) { struct sk_buff *skb = mt7603_mcu_msg_alloc(NULL, 0); return mt7603_mcu_msg_send(dev, skb, -MCU_CMD_RESTART_DL_REQ, MCU_Q_NA); } static int mt7603_load_firmware(struct mt7603_dev *dev) { const struct firmware *fw; const struct mt7603_fw_trailer *hdr; const char *firmware; int dl_len; u32 addr, val; int ret; if (is_mt7628(dev)) { if (mt76xx_rev(dev) == MT7628_REV_E1) firmware = MT7628_FIRMWARE_E1; else firmware = MT7628_FIRMWARE_E2; } else { if (mt76xx_rev(dev) < MT7603_REV_E2) firmware = MT7603_FIRMWARE_E1; else firmware = MT7603_FIRMWARE_E2; } ret = request_firmware(&fw, firmware, dev->mt76.dev); if (ret) return ret; if (!fw || !fw->data || fw->size < sizeof(*hdr)) { dev_err(dev->mt76.dev, "Invalid firmware\n"); ret = -EINVAL; goto out; } hdr = (const struct mt7603_fw_trailer *)(fw->data + fw->size - sizeof(*hdr)); dev_info(dev->mt76.dev, "Firmware Version: %.10s\n", hdr->fw_ver); dev_info(dev->mt76.dev, "Build Time: %.15s\n", hdr->build_date); addr = mt7603_reg_map(dev, 0x50012498); mt76_wr(dev, addr, 0x5); mt76_wr(dev, addr, 0x5); udelay(1); /* switch to bypass mode */ mt76_rmw(dev, MT_SCH_4, MT_SCH_4_FORCE_QID, MT_SCH_4_BYPASS | FIELD_PREP(MT_SCH_4_FORCE_QID, 5)); val = mt76_rr(dev, MT_TOP_MISC2); if (val & BIT(1)) { dev_info(dev->mt76.dev, "Firmware already running...\n"); goto running; } if (!mt76_poll_msec(dev, MT_TOP_MISC2, BIT(0) | BIT(1), BIT(0), 500)) { dev_err(dev->mt76.dev, "Timeout waiting for ROM code to become ready\n"); ret = -EIO; goto out; } dl_len = le32_to_cpu(hdr->dl_len) + 4; ret = mt7603_mcu_init_download(dev, MCU_FIRMWARE_ADDRESS, dl_len); if (ret) { dev_err(dev->mt76.dev, "Download request failed\n"); goto out; } ret = mt7603_mcu_send_firmware(dev, fw->data, dl_len); if (ret) { dev_err(dev->mt76.dev, "Failed to send firmware to device\n"); goto out; } ret = mt7603_mcu_start_firmware(dev, MCU_FIRMWARE_ADDRESS); if (ret) { dev_err(dev->mt76.dev, "Failed to start firmware\n"); goto out; } if (!mt76_poll_msec(dev, MT_TOP_MISC2, BIT(1), BIT(1), 500)) { dev_err(dev->mt76.dev, "Timeout waiting for firmware to initialize\n"); ret = -EIO; goto out; } running: mt76_clear(dev, MT_SCH_4, MT_SCH_4_FORCE_QID | MT_SCH_4_BYPASS); mt76_set(dev, MT_SCH_4, BIT(8)); mt76_clear(dev, MT_SCH_4, BIT(8)); dev->mcu_running = true; dev_info(dev->mt76.dev, "firmware init done\n"); out: release_firmware(fw); return ret; } int mt7603_mcu_init(struct mt7603_dev *dev) { mutex_init(&dev->mt76.mmio.mcu.mutex); return mt7603_load_firmware(dev); }
int mt76_phy_set_channel(struct mt76_dev *dev, struct cfg80211_chan_def *chandef) { struct ieee80211_channel *chan = chandef->chan; bool scan = test_bit(MT76_SCANNING, &dev->state); enum ieee80211_band band = chan->band; u8 channel; u32 ext_cca_chan[4] = { [0] = MT76_SET(MT_EXT_CCA_CFG_CCA0, 0) | MT76_SET(MT_EXT_CCA_CFG_CCA1, 1) | MT76_SET(MT_EXT_CCA_CFG_CCA2, 2) | MT76_SET(MT_EXT_CCA_CFG_CCA3, 3) | MT76_SET(MT_EXT_CCA_CFG_CCA_MASK, BIT(0)), [1] = MT76_SET(MT_EXT_CCA_CFG_CCA0, 1) | MT76_SET(MT_EXT_CCA_CFG_CCA1, 0) | MT76_SET(MT_EXT_CCA_CFG_CCA2, 2) | MT76_SET(MT_EXT_CCA_CFG_CCA3, 3) | MT76_SET(MT_EXT_CCA_CFG_CCA_MASK, BIT(1)), [2] = MT76_SET(MT_EXT_CCA_CFG_CCA0, 2) | MT76_SET(MT_EXT_CCA_CFG_CCA1, 3) | MT76_SET(MT_EXT_CCA_CFG_CCA2, 1) | MT76_SET(MT_EXT_CCA_CFG_CCA3, 0) | MT76_SET(MT_EXT_CCA_CFG_CCA_MASK, BIT(2)), [3] = MT76_SET(MT_EXT_CCA_CFG_CCA0, 3) | MT76_SET(MT_EXT_CCA_CFG_CCA1, 2) | MT76_SET(MT_EXT_CCA_CFG_CCA2, 1) | MT76_SET(MT_EXT_CCA_CFG_CCA3, 0) | MT76_SET(MT_EXT_CCA_CFG_CCA_MASK, BIT(3)), }; int ch_group_index; u8 bw, bw_index; int freq, freq1; int ret; u8 sifs = 13; dev->chandef = *chandef; dev->cal.channel_cal_done = false; freq = chandef->chan->center_freq; freq1 = chandef->center_freq1; channel = chan->hw_value; switch (chandef->width) { case NL80211_CHAN_WIDTH_40: bw = 1; if (freq1 > freq) { bw_index = 1; ch_group_index = 0; } else { bw_index = 3; ch_group_index = 1; } channel += 2 - ch_group_index * 4; break; case NL80211_CHAN_WIDTH_80: ch_group_index = (freq - freq1 + 30) / 20; if (WARN_ON(ch_group_index < 0 || ch_group_index > 3)) ch_group_index = 0; bw = 2; bw_index = ch_group_index; channel += 6 - ch_group_index * 4; break; default: bw = 0; bw_index = 0; ch_group_index = 0; break; } mt76_read_rx_gain(dev); mt76_phy_set_txpower_regs(dev, band); mt76_configure_tx_delay(dev, band, bw); mt76_phy_set_txpower(dev); mt76_apply_rate_power_table(dev); mt76_set_rx_chains(dev); mt76_phy_set_band(dev, chan->band, ch_group_index & 1); mt76_phy_set_bw(dev, chandef->width, ch_group_index); mt76_set_tx_dac(dev); mt76_rmw(dev, MT_EXT_CCA_CFG, (MT_EXT_CCA_CFG_CCA0 | MT_EXT_CCA_CFG_CCA1 | MT_EXT_CCA_CFG_CCA2 | MT_EXT_CCA_CFG_CCA3 | MT_EXT_CCA_CFG_CCA_MASK), ext_cca_chan[ch_group_index]); if (chandef->width >= NL80211_CHAN_WIDTH_40) sifs++; mt76_rmw_field(dev, MT_XIFS_TIME_CFG, MT_XIFS_TIME_CFG_OFDM_SIFS, sifs); ret = mt76_mcu_set_channel(dev, channel, bw, bw_index, scan); if (ret) return ret; mt76_mcu_init_gain(dev, channel, dev->cal.rx.mcu_gain, true); /* Enable LDPC Rx */ if (mt76xx_rev(dev) >= MT76XX_REV_E3) mt76_set(dev, MT_BBP(RXO, 13), BIT(10)); if (!dev->cal.init_cal_done) { u8 val = mt76_eeprom_get(dev, MT_EE_BT_RCAL_RESULT); if (val != 0xff) mt76_mcu_calibrate(dev, MCU_CAL_R, 0); } mt76_mcu_calibrate(dev, MCU_CAL_RXDCOC, channel); /* Rx LPF calibration */ if (!dev->cal.init_cal_done) mt76_mcu_calibrate(dev, MCU_CAL_RC, 0); dev->cal.init_cal_done = true; mt76_wr(dev, MT_BBP(AGC, 61), 0xFF64A4E2); mt76_wr(dev, MT_BBP(AGC, 7), 0x08081010); mt76_wr(dev, MT_BBP(AGC, 11), 0x00000404); mt76_wr(dev, MT_BBP(AGC, 2), 0x00007070); mt76_wr(dev, MT_TXOP_CTRL_CFG, 0x04101B3F); if (scan) return 0; dev->cal.low_gain = -1; mt76_phy_channel_calibrate(dev, true); mt76_get_agc_gain(dev, dev->cal.agc_gain_init); ieee80211_queue_delayed_work(dev->hw, &dev->cal_work, MT_CALIBRATE_INTERVAL); return 0; } static void mt76_phy_tssi_compensate(struct mt76_dev *dev) { struct ieee80211_channel *chan = dev->chandef.chan; struct mt76_tx_power_info txp; struct mt76_tssi_comp t = {}; if (!dev->cal.tssi_cal_done) return; if (dev->cal.tssi_comp_done) { /* TSSI trigger */ t.cal_mode = BIT(0); mt76_mcu_tssi_comp(dev, &t); } else { if (!(mt76_rr(dev, MT_BBP(CORE, 34)) & BIT(4))) return; mt76_get_power_info(dev, &txp); if (mt76_ext_pa_enabled(dev, chan->band)) t.pa_mode = 1; t.cal_mode = BIT(1); t.slope0 = txp.chain[0].tssi_slope; t.offset0 = txp.chain[0].tssi_offset; t.slope1 = txp.chain[1].tssi_slope; t.offset1 = txp.chain[1].tssi_offset; dev->cal.tssi_comp_done = true; mt76_mcu_tssi_comp(dev, &t); if (t.pa_mode || dev->cal.dpd_cal_done) return; msleep(10); mt76_mcu_calibrate(dev, MCU_CAL_DPD, chan->hw_value); dev->cal.dpd_cal_done = true; } } static void mt76_phy_temp_compensate(struct mt76_dev *dev) { struct mt76_temp_comp t; int temp, db_diff; if (mt76_get_temp_comp(dev, &t)) return; temp = mt76_get_field(dev, MT_TEMP_SENSOR, MT_TEMP_SENSOR_VAL); temp -= t.temp_25_ref; temp = (temp * 1789) / 1000 + 25; dev->cal.temp = temp; if (temp > 25) db_diff = (temp - 25) / t.high_slope; else db_diff = (25 - temp) / t.low_slope; db_diff = min(db_diff, t.upper_bound); db_diff = max(db_diff, t.lower_bound); mt76_rmw_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP, db_diff * 2); mt76_rmw_field(dev, MT_TX_ALC_CFG_2, MT_TX_ALC_CFG_2_TEMP_COMP, db_diff * 2); } void mt76_phy_calibrate(struct work_struct *work) { struct mt76_dev *dev; dev = container_of(work, struct mt76_dev, cal_work.work); mt76_phy_channel_calibrate(dev, false); mt76_phy_tssi_compensate(dev); mt76_phy_temp_compensate(dev); mt76_phy_update_channel_gain(dev); ieee80211_queue_delayed_work(dev->hw, &dev->cal_work, MT_CALIBRATE_INTERVAL); } int mt76_phy_start(struct mt76_dev *dev) { int ret; ret = mt76_mcu_set_radio_state(dev, true); if (ret) return ret; mt76_mcu_load_cr(dev, MT_RF_BBP_CR, 0, 0); return ret; }