mali_error kbase_pm_powerup(struct kbase_device *kbdev)
{
unsigned long flags;
mali_error ret;
unsigned int code; //mtk
unsigned int gpu_efuse;
KBASE_DEBUG_ASSERT(kbdev != NULL);
mutex_lock(&kbdev->pm.lock);
/* A suspend won't happen during startup/insmod */
KBASE_DEBUG_ASSERT(!kbase_pm_is_suspending(kbdev));
/* Power up the GPU, don't enable IRQs as we are not ready to receive them. */
ret = kbase_pm_init_hw(kbdev, MALI_FALSE);
if (ret != MALI_ERROR_NONE) {
mutex_unlock(&kbdev->pm.lock);
return ret;
}
kbasep_pm_read_present_cores(kbdev);
// mtk
code = mt_get_chip_hw_code();
if (0x321 == code) // Denali-1(6735)
{
// read GPU efuse info.
gpu_efuse = (get_devinfo_with_index(3) >> 7)&0x01;
if( gpu_efuse == 1 )
kbdev->pm.debug_core_mask = (u64)1; // 1-core
else
kbdev->pm.debug_core_mask = (u64)3; // 2-core
}
static int pm_callback_power_on(struct kbase_device *kbdev)
{
#ifdef CONFIG_MALI_MIDGARD_DVFS
int touch_boost_flag, touch_boost_id;
#endif /* CONFIG_MALI_MIDGARD_DVFS */
unsigned int current_gpu_freq_idx;
#ifndef CONFIG_MTK_CLKMGR
int ret;
#endif
unsigned int code;
code = mt_get_chip_hw_code();
mt_gpufreq_voltage_enable_set(1);
#ifdef ENABLE_COMMON_DVFS
ged_dvfs_gpu_clock_switch_notify(1);
#endif
#ifdef CONFIG_MTK_CLKMGR
enable_clock( MT_CG_DISP0_SMI_COMMON, "GPU");
enable_clock( MT_CG_MFG_BG3D, "GPU");
#endif
g_power_status = 1; // the power status is "power on".
mt_gpufreq_target(g_power_off_gpu_freq_idx);
current_gpu_freq_idx = mt_gpufreq_get_cur_freq_index();
if( current_gpu_freq_idx > g_power_off_gpu_freq_idx)
pr_debug("MALI: GPU freq. can't switch to idx=%d\n", g_power_off_gpu_freq_idx );
mtk_get_touch_boost_flag( &touch_boost_flag, &touch_boost_id);
if(touch_boost_flag > 0)
{
mt_gpufreq_target(touch_boost_id);
mtk_clear_touch_boost_flag();
}
/* Nothing is needed on VExpress, but we may have destroyed GPU state (if the below HARD_RESET code is active) */
return 1;
}
const bool cmdq_driver_support_wait_and_receive_event_in_same_tick(void)
{
#ifdef CMDQ_USE_LEGACY
const unsigned int code = mt_get_chip_hw_code();
CHIP_SW_VER ver = mt_get_chip_sw_ver();
bool support = false;
if (0x6795 == code) {
support = true;
} else if (CHIP_SW_VER_02 <= ver) {
/* SW V2 */
support = true;
} else if (CHIP_SW_VER_01 <= ver) {
support = false;
}
return support;
#else
return true;
#endif
}
static int pm_callback_power_on(struct kbase_device *kbdev)
{
int touch_boost_flag, touch_boost_id;
unsigned int current_gpu_freq_idx;
#ifndef CONFIG_MTK_CLKMGR
int ret;
#endif
unsigned int code = mt_get_chip_hw_code();
mt_gpufreq_voltage_enable_set(1);
if (0x321 == code) {
// do something for Denali-1(6735)
#ifdef CONFIG_MTK_CLKMGR
enable_clock( MT_CG_DISP0_SMI_COMMON, "GPU");
enable_clock( MT_CG_MFG_BG3D, "GPU");
#else
ret = clk_prepare_enable(kbdev->clk_display_scp);
if (ret)
{
pr_debug("MALI: clk_prepare_enable failed when enabling display MTCMOS");
}
ret = clk_prepare_enable(kbdev->clk_smi_common);
if (ret)
{
pr_debug("MALI: clk_prepare_enable failed when enabling display smi_common clock");
}
ret = clk_prepare_enable(kbdev->clk_mfg_scp);
if (ret)
{
pr_debug("MALI: clk_prepare_enable failed when enabling mfg MTCMOS");
}
ret = clk_prepare_enable(kbdev->clk_mfg);
if (ret)
{
pr_debug("MALI: clk_prepare_enable failed when enabling mfg clock");
}
#endif
} else if (0x335 == code) {
// do something for Denali-2(6735M)
#ifdef CONFIG_MTK_CLKMGR
enable_clock( MT_CG_DISP0_SMI_COMMON, "GPU");
enable_clock( MT_CG_MFG_BG3D, "GPU");
#endif /* CONFIG_MTK_CLKMGR */
} else if (0x337 == code) {
// do something for Denali-3(6753)
#ifdef CONFIG_MTK_CLKMGR
enable_clock( MT_CG_DISP0_SMI_COMMON, "GPU");
enable_clock( MT_CG_MFG_BG3D, "GPU");
#endif /* CONFIG_MTK_CLKMGR */
} else {
// unknown chip ID, error !!
#ifdef CONFIG_MTK_CLKMGR
enable_clock( MT_CG_DISP0_SMI_COMMON, "GPU");
enable_clock( MT_CG_MFG_BG3D, "GPU");
#endif /* CONFIG_MTK_CLKMGR */
}
g_power_status = 1; // the power status is "power on".
mt_gpufreq_target(g_power_off_gpu_freq_idx);
current_gpu_freq_idx = mt_gpufreq_get_cur_freq_index();
if( current_gpu_freq_idx > g_power_off_gpu_freq_idx)
pr_debug("MALI: GPU freq. can't switch to idx=%d\n", g_power_off_gpu_freq_idx );
mtk_get_touch_boost_flag( &touch_boost_flag, &touch_boost_id);
if(g_type_T==1)
{
if(touch_boost_flag > 0)
{
mt_gpufreq_target(1);
mtk_clear_touch_boost_flag();
}
}
else
{
if(touch_boost_flag > 0)
{
mt_gpufreq_target(touch_boost_id);
mtk_clear_touch_boost_flag();
}
}
/* Nothing is needed on VExpress, but we may have destroyed GPU state (if the below HARD_RESET code is active) */
return 1;
}
static void pm_callback_power_off(struct kbase_device *kbdev)
{
unsigned int uiCurrentFreqCount;
volatile int polling_count = 100000;
volatile int i = 0;
unsigned int code;
/// 1. Delay 0.01ms before power off
for (i=0; i < DELAY_LOOP_COUNT;i++);
if (DELAY_LOOP_COUNT != i)
{
pr_debug("[MALI] power off delay error!\n");
}
/// 2. Polling the MFG_DEBUG_REG for checking GPU IDLE before MTCMOS power off (0.1ms)
MFG_WRITE32(0x3, MFG_DEBUG_CTRL_REG);
do {
/// 0x13000184[2]
/// 1'b1: bus idle
/// 1'b0: bus busy
if (MFG_READ32(MFG_DEBUG_STAT_REG) & MFG_BUS_IDLE_BIT)
{
/// pr_debug("[MALI]MFG BUS already IDLE! Ready to power off, %d\n", polling_count);
break;
}
} while (polling_count--);
if (polling_count <=0)
{
pr_debug("[MALI]!!!!MFG(GPU) subsys is still BUSY!!!!!, polling_count=%d\n", polling_count);
}
#if HARD_RESET_AT_POWER_OFF
/* Cause a GPU hard reset to test whether we have actually idled the GPU
* and that we properly reconfigure the GPU on power up.
* Usually this would be dangerous, but if the GPU is working correctly it should
* be completely safe as the GPU should not be active at this point.
* However this is disabled normally because it will most likely interfere with
* bus logging etc.
*/
//KBASE_TRACE_ADD(kbdev, CORE_GPU_HARD_RESET, NULL, NULL, 0u, 0);
kbase_os_reg_write(kbdev, GPU_CONTROL_REG(GPU_COMMAND), GPU_COMMAND_HARD_RESET);
#endif
/// Polling the MFG_DEBUG_REG for checking GPU IDLE before MTCMOS power off (0.1ms)
MFG_WRITE32(0x3, MFG_DEBUG_CTRL_REG);
do {
/// 0x13000184[2]
/// 1'b1: bus idle
/// 1'b0: bus busy
if (MFG_READ32(MFG_DEBUG_STAT_REG) & MFG_BUS_IDLE_BIT)
{
/// pr_debug("[MALI]MFG BUS already IDLE! Ready to power off, %d\n", polling_count);
break;
}
} while (polling_count--);
if (polling_count <=0)
{
pr_debug("[MALI]!!!!MFG(GPU) subsys is still BUSY!!!!!, polling_count=%d\n", polling_count);
}
g_power_status = 0; // the power status is "power off".
g_power_off_gpu_freq_idx = mt_gpufreq_get_cur_freq_index(); // record current freq. index.
//pr_debug("MALI: GPU power off freq idx : %d\n",g_power_off_gpu_freq_idx );
#if 1
uiCurrentFreqCount = mt_gpufreq_get_dvfs_table_num(); // get freq. table size
mt_gpufreq_target(uiCurrentFreqCount-1); // set gpu to lowest freq.
#endif
code = mt_get_chip_hw_code();
/* MTK clock modified */
if (0x321 == code) {
// do something for Denali-1(6735)
#ifdef CONFIG_MTK_CLKMGR
disable_clock( MT_CG_MFG_BG3D, "GPU");
disable_clock( MT_CG_DISP0_SMI_COMMON, "GPU");
#else
clk_disable_unprepare(kbdev->clk_mfg);
clk_disable_unprepare(kbdev->clk_mfg_scp);
clk_disable_unprepare(kbdev->clk_smi_common);
clk_disable_unprepare(kbdev->clk_display_scp);
#endif
} else if (0x335 == code) {
// do something for Denali-2(6735M)
#ifdef CONFIG_MTK_CLKMGR
disable_clock( MT_CG_MFG_BG3D, "GPU");
disable_clock( MT_CG_DISP0_SMI_COMMON, "GPU");
#endif /* CONFIG_MTK_CLKMGR */
} else if (0x337 == code) {
// do something for Denali-3(6753)
#ifdef CONFIG_MTK_CLKMGR
disable_clock( MT_CG_MFG_BG3D, "GPU");
disable_clock( MT_CG_DISP0_SMI_COMMON, "GPU");
#endif /* CONFIG_MTK_CLKMGR */
} else {
// unknown chip ID, error !!
#ifdef CONFIG_MTK_CLKMGR
disable_clock( MT_CG_MFG_BG3D, "GPU");
disable_clock( MT_CG_DISP0_SMI_COMMON, "GPU");
#endif /* CONFIG_MTK_CLKMGR */
}
mt_gpufreq_voltage_enable_set(0);
}
void mtk_xhci_ck_timer_init(struct xhci_hcd *xhci)
{
void __iomem *addr;
u32 temp = 0;
int num_u3_port;
unsigned int hw_code = mt_get_chip_hw_code();
CHIP_SW_VER sw_code = mt_get_chip_sw_ver();
mtk_xhci_mtk_log("hw code(0x%x), sw_code(0x%x)\n", hw_code, sw_code);
if (0x6595 == hw_code) {
/* The sys125_ck = 1/2 sys_ck = 62.5MHz */
addr = (void __iomem *)_SSUSB_SYS_CK_CTRL(xhci->sif_regs);
temp = readl(addr);
temp |= SSUSB_SYS_CK_DIV2_EN;
writel(temp, addr);
mtk_xhci_mtk_log("mu3d sys_clk, addr 0x%p, value 0x%x\n",
(void *)_SSUSB_SYS_CK_CTRL(xhci->sif_regs), readl((__u32 __iomem *)_SSUSB_SYS_CK_CTRL(xhci->sif_regs)));
num_u3_port = SSUSB_U3_PORT_NUM(readl((void __iomem *)_SSUSB_IP_CAP(xhci->sif_regs)));
if (num_u3_port) {
#if 0
//set MAC reference clock speed
addr = (void __iomem *) (_SSUSB_U3_MAC_BASE(xhci->base_regs) + U3_UX_EXIT_LFPS_TIMING_PAR);
temp = readl(addr);
temp &= ~(0xff << U3_RX_UX_EXIT_LFPS_REF_OFFSET);
temp |= (U3_RX_UX_EXIT_LFPS_REF << U3_RX_UX_EXIT_LFPS_REF_OFFSET);
writel(temp, addr);
addr = (void __iomem *)(_SSUSB_U3_MAC_BASE(xhci->base_regs) + U3_REF_CK_PAR);
temp = readl(addr);
temp &= ~(0xff);
temp |= U3_REF_CK_VAL;
writel(temp, addr);
#endif
/* set U3 MAC SYS_CK */
addr = (void __iomem *)(_SSUSB_U3_SYS_BASE(xhci->base_regs) + U3_TIMING_PULSE_CTRL);
temp = readl(addr);
temp &= ~(0xff);
temp |= MTK_CNT_1US_VALUE;
writel(temp, addr);
}
/* set U2 MAC SYS_CK */
addr = (void __iomem *)(_SSUSB_U2_SYS_BASE(xhci->base_regs) + USB20_TIMING_PARAMETER);
temp &= ~(0xff);
temp |= MTK_TIME_VALUE_1US;
writel(temp, addr);
mtk_xhci_mtk_log("mu3d u2 mac sys_clk, addr 0x%p, value 0x%x\n",
(void *)(_SSUSB_U2_SYS_BASE(xhci->base_regs) + USB20_TIMING_PARAMETER),
readl((void __iomem *)(_SSUSB_U2_SYS_BASE(xhci->base_regs) + (unsigned long)USB20_TIMING_PARAMETER)));
#if 0
if (num_u3_port) {
//set LINK_PM_TIMER=3
addr = (void __iomem *)(_SSUSB_U3_SYS_BASE(xhci->base_regs) + LINK_PM_TIMER);
temp = readl(addr);
temp &= ~(0xf);
temp |= MTK_PM_LC_TIMEOUT_VALUE;
writel(temp, addr);
}
#endif
}
}
