unsigned long long notrace sched_clock(void)
{
struct clocksource *cs = &mt6582_gpt.clocksource;
cycle_t cycles;
if(0 == g_clksrc_init)
{
return jiffy_sched_clock_read();
}
else
{
cycles = mt_gpt_read(cs);
cycles *= 1000 << 1;
#ifndef CONFIG_MT6582_FPGA
do_div(cycles, 13 << 1);
#else
do_div(cycles, 6 << 1);
#endif
return cycles;
//return cyc_to_ns(cycles,cs->mult, cs->shift);
}
}
static void __init mt_gpt_init(struct device_node *node)
{
int i;
u32 freq;
unsigned long save_flags;
gpt_update_lock(save_flags);
/* freq=SYS_CLK_RATE */
if (of_property_read_u32(node, "clock-frequency", &freq))
pr_err("clock-frequency not set in the .dts file");
/* Setup IRQ numbers */
xgpt_timers.tmr_irq = irq_of_parse_and_map(node, 0);
/* Setup IO addresses */
xgpt_timers.tmr_regs = of_iomap(node, 0);
boot_time_value = xgpt_boot_up_time(); /*record the time when init GPT*/
pr_alert("mt_gpt_init: tmr_regs=0x%lx, tmr_irq=%d, freq=%d\n",
(unsigned long)xgpt_timers.tmr_regs, xgpt_timers.tmr_irq, freq);
gpt_devs_init();
for (i = 0; i < NR_GPTS; i++)
__gpt_reset(&gpt_devs[i]);
setup_clksrc(freq);
setup_irq(xgpt_timers.tmr_irq, &gpt_irq);
setup_clkevt(freq);
/* use cpuxgpt as syscnt */
setup_syscnt();
pr_alert("mt_gpt_init: get_cnt_GPT2=%lld\n", mt_gpt_read(NULL)); /* /TODO: remove */
gpt_update_unlock(save_flags);
}
static u64 notrace mt_read_sched_clock(void)
{
return mt_gpt_read(NULL);
}
static cycle_t mt_read_sched_clock_cc(const struct cyclecounter *cc)
{
return mt_gpt_read(NULL);
}
static cycle_t notrace mt_read_sched_clock(void)
{
return mt_gpt_read(NULL);
}