/*============================================================================*/
void uart_handshake_init(void)
{
/* switch to meta port */
mtk_serial_set_current_uart(CFG_UART_META);
/* if meta and log ports are SAME, need to re-init meta port with
* different baudrate and disable log output during handshake to avoid
* influence.
*/
if (CFG_UART_META == CFG_UART_LOG) {
/* to prevent sync error with PC */
gpt_busy_wait_us(160);
/* init to meta baudrate */
mtk_uart_init(UART_SRC_CLK_FRQ, CFG_META_BAUDRATE);
/* disable log so that log message will be kept in log buffer */
log_buf_ctrl(0);
log_ctrl(0);
}
/* send meta ready to tool via meta port first then let meta port to listen
* meta response in the background to reduce the handshake wait time later.
*/
uart_send((u8*)HSHK_COM_READY, strlen(HSHK_COM_READY));
mtk_serial_set_current_uart(CFG_UART_LOG);
g_meta_ready_start_time = get_timer(0);
}
void platform_error_handler(void)
{
/* if log is disabled, re-init log port and enable it */
if (log_status() == 0) {
mtk_uart_init(UART_SRC_CLK_FRQ, CFG_LOG_BAUDRATE);
log_ctrl(1);
}
print("%s preloader fatal error...\n", MOD);
/* enter emergency download mode */
platform_emergency_download(CFG_EMERGENCY_DL_TIMEOUT_MS);
while(1);
}
static bool uart_handshake_handler(struct bldr_command_handler *handler)
{
bool result = TRUE;
bool avail;
int sync_time;
uint8 buf[HSHK_TOKEN_SZ + 1] = {'\0'};
struct bldr_command cmd;
struct bldr_comport comport;
struct comport_ops uart_ops = {.send = uart_send, .recv = uart_recv};
comport.type = COM_UART;
comport.tmo = UART_SYNC_TIME;
comport.ops = &uart_ops;
sync_time = UART_SYNC_TIME - get_timer(g_meta_ready_start_time);
sync_time = sync_time <= 0 ? 5 : sync_time;
sync_time = sync_time > UART_SYNC_TIME ? UART_SYNC_TIME : sync_time;
/* detect tool existence */
mtk_serial_set_current_uart(CFG_UART_META);
avail = uart_listen(&comport, buf, HSHK_TOKEN_SZ, 1, sync_time);
mtk_serial_set_current_uart(CFG_UART_LOG);
if (!avail) {
result = FALSE;
goto exit;
}
cmd.data = buf;
cmd.len = HSHK_TOKEN_SZ;
result = handler->cb(handler, &cmd, &comport);
exit:
if (CFG_UART_META == CFG_UART_LOG) {
/* enable log message again since no tool is connected */
if (result != TRUE) {
/* init to log baudrate */
mtk_uart_init(UART_SRC_CLK_FRQ, CFG_LOG_BAUDRATE);
/* enable log and flush the log buffer if log message available */
log_ctrl(1);
}
}
print("\n");
print("%s <UART> wait sync time %dms->%dms\n", MOD, UART_SYNC_TIME, sync_time);
print("%s <UART> receieved data: (%s)\n", MOD, buf);
return result;
}
void main(u32 *arg)
{
struct bldr_command_handler handler;
u32 jump_addr;
/* get the bldr argument */
bldr_param = (bl_param_t *)*arg;
mtk_uart_init(UART_SRC_CLK_FRQ, CFG_LOG_BAUDRATE);
bldr_pre_process();
#ifdef HW_INIT_ONLY
bldr_wait_forever();
#endif
handler.priv = NULL;
handler.attr = 0;
handler.cb = bldr_cmd_handler;
BOOTING_TIME_PROFILING_LOG("before bldr_handshake");
bldr_handshake(&handler);
BOOTING_TIME_PROFILING_LOG("bldr_handshake");
#if !CFG_FPGA_PLATFORM
/* security check */
sec_lib_read_secro();
sec_boot_check();
device_APC_dom_setup();
#endif
BOOTING_TIME_PROFILING_LOG("sec_boot_check");
#if CFG_ATF_SUPPORT
trustzone_pre_init();
#endif
if (0 != bldr_load_images(&jump_addr)) {
print("%s Second Bootloader Load Failed\n", MOD);
goto error;
}
bldr_post_process();
#ifdef SLT
mt_usb_phy_recover();
//mu3d_hal_rst_dev();
#endif
#if CFG_ATF_SUPPORT
trustzone_post_init();
#endif
//Yi-Lung: recover pmic normal reset
platform_pmic_full_reset_disable();
#if CFG_LOAD_SLT_AARCH64_KERNEL
if (0 == aarch64_slt_done())
{
*(unsigned int*) AARCH64_SLT_DONE_ADDRESS = AARCH64_SLT_DONE_MAGIC;
jump_addr = CFG_BOOTA64_MEMADDR;
//set up slave cpu reset address
*(unsigned int*) 0x10200040 = CFG_BOOTA64_MEMADDR; //cpu1
*(unsigned int*) 0x10200048 = CFG_BOOTA64_MEMADDR; //cpu2
*(unsigned int*) 0x10200050 = CFG_BOOTA64_MEMADDR; //cpu3
*(unsigned int*) 0x10200238 = CFG_BOOTA64_MEMADDR; //cpu4
*(unsigned int*) 0x10200240 = CFG_BOOTA64_MEMADDR; //cpu5
*(unsigned int*) 0x10200248 = CFG_BOOTA64_MEMADDR; //cpu6
*(unsigned int*) 0x10200250 = CFG_BOOTA64_MEMADDR; //cpu7
print("%s Aarch64 Kernel SLT , jump to 64 bit kernel, address: 0x%x\n", MOD,jump_addr);
bldr_jump64(jump_addr, (u32)&bootarg, sizeof(boot_arg_t));
}
#endif
/* 64S3,32S1,32S1 (MTK_ATF_BOOT_OPTION = 0)
* re-loader jump to LK directly and then LK jump to kernel directly */
#if CFG_ATF_SUPPORT
if ( BOOT_OPT_64S3 == bootarg.smc_boot_opt &&
BOOT_OPT_32S1 == bootarg.lk_boot_opt &&
BOOT_OPT_32S1 == bootarg.kernel_boot_opt) {
print("%s 64S3,32S1,32S1, jump to LK\n", MOD);
bldr_jump(jump_addr, (u32)&bootarg, sizeof(boot_arg_t));
} else {
print("%s Others, jump to ATF\n", MOD);
bldr_jump64(jump_addr, (u32)&bootarg, sizeof(boot_arg_t));
}
#else
bldr_jump(jump_addr, (u32)&bootarg, sizeof(boot_arg_t));
#endif
error:
platform_error_handler();
}
void platform_pre_init(void)
{
u32 i2c_ret, pmic_ret;
u32 pwrap_ret=0,i=0;
int pll_ret;
/* 2012/11/27
* Sten
* Add MT6589 MCI downsizer workaround start*/
*(volatile unsigned int*)(0x10001200) |= (0x1);
/* Add MT6589 MCI downsizer workaround end*/
/* init timer */
mtk_timer_init();
/* init boot time */
g_boot_time = get_timer(0);
#if 0 /* FIXME */
/*
* NoteXXX: CPU 1 may not be reset clearly after power-ON.
* Need to apply a S/W workaround to manualy reset it first.
*/
{
U32 val;
val = DRV_Reg32(0xC0009010);
DRV_WriteReg32(0xC0009010, val | 0x2);
gpt_busy_wait_us(10);
DRV_WriteReg32(0xC0009010, val & ~0x2);
gpt_busy_wait_us(10);
}
#ifndef SLT_BOOTLOADER
/* power off cpu1 for power saving */
power_off_cpu1();
#endif
#endif
/* init pll */
pll_ret = mt_pll_init();
/*GPIO init*/
mt_gpio_init();
/* init uart baudrate when pll on */
mtk_uart_init(UART_SRC_CLK_FRQ, CFG_LOG_BAUDRATE);
if (pll_ret != 0)
print("MEMPLL 3PLL mode calibration fail\n");
/* init pmic i2c interface and pmic */
i2c_ret = i2c_v1_init();
//retry 3 times for pmic wrapper init
pwrap_init_preloader();
pmic_ret = pmic6320_init();
//enable long press reboot function***************
#ifndef EVB_PLATFORM
#ifdef KPD_PMIC_LPRST_TD
#ifdef ONEKEY_REBOOT_NORMAL_MODE_PL
pmic_config_interface(TOP_RST_MISC, 0x01, PMIC_RG_PWRKEY_RST_EN_MASK, PMIC_RG_PWRKEY_RST_EN_SHIFT);//pmic_config_interface(TOP_RST_MISC, 0x01, PMIC_RG_PWRKEY_RST_EN_MASK, PMIC_RG_PWRKEY_RST_EN_SHIFT);
pmic_config_interface(GPIO_SMT_CON3,0x01, PMIC_RG_HOMEKEY_PUEN_MASK, PMIC_RG_HOMEKEY_PUEN_SHIFT);//pull up homekey pin of PMIC for 89 project
pmic_config_interface(TOP_RST_MISC, (U32)KPD_PMIC_LPRST_TD, PMIC_RG_PWRKEY_RST_TD_MASK, PMIC_RG_PWRKEY_RST_TD_SHIFT);
#endif
#ifdef TWOKEY_REBOOT_NORMAL_MODE_PL
pmic_config_interface(TOP_RST_MISC, 0x01, PMIC_RG_PWRKEY_RST_EN_MASK, PMIC_RG_PWRKEY_RST_EN_SHIFT);//pmic package function for long press reboot function setting//
pmic_config_interface(TOP_RST_MISC, 0x01, PMIC_RG_HOMEKEY_RST_EN_MASK, PMIC_RG_HOMEKEY_RST_EN_SHIFT);;//pmic_config_interface(TOP_RST_MISC, 0x01, PMIC_RG_HOMEKEY_RST_EN_MASK, PMIC_RG_HOMEKEY_RST_EN_SHIFT);
pmic_config_interface(GPIO_SMT_CON3,0x01, PMIC_RG_HOMEKEY_PUEN_MASK, PMIC_RG_HOMEKEY_PUEN_SHIFT);//pull up homekey pin of PMIC for 89 project
pmic_config_interface(TOP_RST_MISC, (U32)KPD_PMIC_LPRST_TD, PMIC_RG_PWRKEY_RST_TD_MASK, PMIC_RG_PWRKEY_RST_TD_SHIFT);
#endif
#endif
#endif
//************************************************
print("%s Init I2C: %s(%d)\n", MOD, i2c_ret ? "FAIL" : "OK", i2c_ret);
print("%s Init PWRAP: %s(%d)\n", MOD, pwrap_ret ? "FAIL" : "OK", pwrap_ret);
print("%s Init PMIC: %s(%d)\n", MOD, pmic_ret ? "FAIL" : "OK", pmic_ret);
print("%s chip[%x]\n", MOD, platform_chip_ver());
}
void platform_pre_init(void)
{
u32 ret;
u32 pmic_ret;
u32 pwrap_ret,i;
#ifdef PL_PROFILING
u32 profiling_time;
profiling_time = 0;
#endif
pwrap_ret = 0;
i = 0;
ret = 0;
/* init timer */
mtk_timer_init();
/* init boot time */
g_boot_time = get_timer(0);
#if 0 /* FIXME */
/*
* NoteXXX: CPU 1 may not be reset clearly after power-ON.
* Need to apply a S/W workaround to manualy reset it first.
*/
{
U32 val;
val = DRV_Reg32(0xC0009010);
DRV_WriteReg32(0xC0009010, val | 0x2);
gpt_busy_wait_us(10);
DRV_WriteReg32(0xC0009010, val & ~0x2);
gpt_busy_wait_us(10);
}
#ifndef SLT_BOOTLOADER
/* power off cpu1 for power saving */
power_off_cpu1();
#endif
#endif
ptp_init1();
/* move pll code to audio_sys_ram */
memcpy((char *)&Image$$PLL_INIT$$Base, &__load_start_pll_text,
&__load_stop_pll_text - &__load_start_pll_text);
/* init pll */
/* for memory preserved mode */
// do not init pll/emi in memory preserved mode, due to code is located in EMI
// set all pll except EMI
mtk_pll_init();
/*GPIO init*/
#if (!(CFG_FPGA_PLATFORM)) && defined(DUMMY_AP_BOOTLOADER)
mt_gpio_set_default();
#endif
//set UART1 GPIO to mode1, AP
mt_gpio_init_post(0);
/* init uart baudrate when pll on */
mtk_uart_init(UART_SRC_CLK_FRQ, CFG_LOG_BAUDRATE);
/* init pmic i2c interface and pmic */
/* no need in MT6572*/
//i2c_ret = i2c_v1_init();
//retry 3 times for pmic wrapper init
#ifdef PL_PROFILING
profiling_time = get_timer(0);
#endif
pwrap_init_preloader();
/* check is uart cable in*/
#if (CFG_USB_UART_SWITCH)
platform_vusb_on();
if (is_uart_cable_inserted()) {
print("\n%s Switch to UART Mode\n", MOD);
mt_usb_set_to_uart_mode();
} else {
print("\n%s Keep stay in USB Mode\n", MOD);
}
#endif
if (platform_sram_repair_enable_check())
{
//MM SRAM Repair
ret = MFG_MM_SRAM_repair();
if (ret < 0 )
printf("MFG_MM_SRAM_repair fail\n");
else
printf("MFG_MM_SRAM_repair OK\n");
}
#ifdef PL_PROFILING
printf("#T#pwrap_init=%d\n", get_timer(profiling_time));
profiling_time = get_timer(0); //for next
#endif
pmic_ret = pmic_init();
//enable long press reboot function***************
#ifndef CFG_EVB_PLATFORM
#ifdef KPD_PMIC_LPRST_TD
#ifdef ONEKEY_REBOOT_NORMAL_MODE_PL
printf("ONEKEY_REBOOT_NORMAL_MODE_PL OK\n");
pmic_config_interface(TOP_RST_MISC, 0x01, PMIC_RG_PWRKEY_RST_EN_MASK, PMIC_RG_PWRKEY_RST_EN_SHIFT);//pmic_config_interface(TOP_RST_MISC, 0x01, PMIC_RG_PWRKEY_RST_EN_MASK, PMIC_RG_PWRKEY_RST_EN_SHIFT);
pmic_config_interface(TOP_RST_MISC, (U32)KPD_PMIC_LPRST_TD, PMIC_RG_PWRKEY_RST_TD_MASK, PMIC_RG_PWRKEY_RST_TD_SHIFT);
#endif
#endif
#endif
//************************************************
#ifdef PL_PROFILING
printf("#T#pmic_init=%d\n", get_timer(profiling_time));
#endif
print("%s Init PWRAP: %s(%d)\n", MOD, pwrap_ret ? "FAIL" : "OK", pwrap_ret);
print("%s Init PMIC: %s(%d)\n", MOD, pmic_ret ? "FAIL" : "OK", pmic_ret);
print("%s chip[%x]\n", MOD, platform_chip_ver());
}
