unsigned char nRFAPI_Init(
unsigned char channel,
const unsigned char *mac,
unsigned char mac_size,
unsigned char features
)
{
unsigned char i;
// init lower layer
nRFCMD_Init();
// check validity
if( mac_size<3 ||
mac_size>5 ||
!nRFAPI_DetectChip()
)
return 0;
// update mac
nRFAPI_SetSizeMac(mac_size);
nRFAPI_SetTxMAC(mac,mac_size);
// enables pipe
nRFAPI_SetRxMAC(mac,mac_size,0);
nRFAPI_PipesEnable(ERX_P0);
nRFAPI_PipesAck(0);
// set payload sizes
for(i=0; i<=5; i++)
nRFAPI_SetPipeSizeRX(i,2);
// set TX retry count
nRFAPI_TxRetries(0);
// set selected channel
nRFAPI_SetChannel(channel);
// set Tx power
nRFAPI_SetTxPower(3);
// flush FIFOs
nRFAPI_FlushRX();
nRFAPI_FlushTX();
nRFAPI_SetRxMode(0);
if(features != 0)
nRFAPI_SetFeatures(features);
return 1;
}
uint8_t
nRFAPI_Init (uint8_t channel,
const uint8_t * mac, uint8_t mac_size, uint8_t features)
{
uint8_t i;
// init IO layer of nRF24L01
nRFCMD_Init ();
/* wait for nRF to boot */
pmu_sleep_ms(10);
// check validity
if (mac_size < 3 || mac_size > 5 || !nRFAPI_DetectChip ())
return 0;
// update mac
nRFAPI_SetSizeMac (mac_size);
nRFAPI_SetTxMAC (mac, mac_size);
// enables pipe
nRFAPI_SetRxMAC (mac, mac_size, 0);
nRFAPI_PipesEnable (ERX_P0);
nRFAPI_PipesAck (0);
// set payload sizes
for (i = 0; i <= 5; i++)
nRFAPI_SetPipeSizeRX (i, 16);
// set TX retry count
nRFAPI_TxRetries (0);
// set selected channel
nRFAPI_SetChannel (channel);
// set Tx power
nRFAPI_SetTxPower (3);
// flush FIFOs
nRFAPI_FlushRX ();
nRFAPI_FlushTX ();
if (features != 0)
nRFAPI_SetFeatures (features);
return 1;
}
void
main (void)
{
uint8_t j;
/* configure CPU peripherals */
OSCCON = CONFIG_CPU_OSCCON_SLOW;
OPTION_REG = CONFIG_CPU_OPTION;
PORTA = CONFIG_CPU_PORTA;
PORTC = CONFIG_CPU_PORTC;
TRISA = CONFIG_CPU_TRISA;
TRISC = CONFIG_CPU_TRISC;
WPUA = CONFIG_CPU_WPUA;
WPUC = CONFIG_CPU_WPUC;
ANSELA = CONFIG_CPU_ANSELA;
ANSELC = CONFIG_CPU_ANSELC;
INTE = 0;
CONFIG_PIN_SENSOR = 0;
CONFIG_PIN_TX_POWER = 0;
/* initalize hardware */
timer_init ();
/* verify RF chip */
nRFCMD_Init ();
while(1)
{
nRFCMD_Channel (23);
if(nRFCMD_RegGet (NRF_REG_RF_CH)==23)
{
nRFCMD_Channel (42);
if(nRFCMD_RegGet (NRF_REG_RF_CH)==42)
break;
}
CONFIG_PIN_LED = 1;
sleep_jiffies (JIFFIES_PER_MS (25));
CONFIG_PIN_LED = 0;
sleep_jiffies (JIFFIES_PER_MS (25));
}
/* blink to show readyiness */
for (j = 0; j <= 10; j++)
{
CONFIG_PIN_LED = j & 1;
sleep_jiffies (JIFFIES_PER_MS (25));
}
// switch to listening channel
nRFCMD_Channel (CONFIG_TRACKER_CHANNEL);
while (1)
{
/*
nRFCMD_Listen (JIFFIES_PER_MS (500));
if (!CONFIG_PIN_IRQ)
{
while ((nRFCMD_RegGet (NRF_REG_FIFO_STATUS) &
NRF_FIFO_RX_EMPTY) == 0)
{
// receive raw data
nRFCMD_RegRead (RD_RX_PLOAD, pkt, sizeof (pkt));
nRFCMD_RegPut (NRF_REG_STATUS | WRITE_REG,
NRF_CONFIG_MASK_RX_DR);
CONFIG_PIN_LED = 1;
sleep_jiffies (JIFFIES_PER_MS (100));
}
}
CONFIG_PIN_LED = 1;
// blink for 1ms
sleep_jiffies (JIFFIES_PER_MS (1));
// disable LED
CONFIG_PIN_LED = 0;
*/
for(j=0;j<200;j++)
pwm(10);
for(j=0;j<200;j++)
pwm(30);
}
}
