sint8 nmi_get_otp_mac_address(uint8 *pu8MacAddr, uint8 * pu8IsValid)
{
sint8 ret;
uint32 u32RegValue;
uint8 mac[6];
tstrGpRegs strgp = {0};
ret = nm_read_reg_with_ret(rNMI_GP_REG_0, &u32RegValue);
if(ret != M2M_SUCCESS) goto _EXIT_ERR;
ret = nm_read_block(u32RegValue|0x30000,(uint8*)&strgp,sizeof(tstrGpRegs));
if(ret != M2M_SUCCESS) goto _EXIT_ERR;
u32RegValue = strgp.u32Mac_efuse_mib;
if(!EFUSED_MAC(u32RegValue)) {
M2M_DBG("Default MAC\n");
m2m_memset(pu8MacAddr, 0, 6);
goto _EXIT_ERR;
}
M2M_DBG("OTP MAC\n");
u32RegValue >>=16;
ret = nm_read_block(u32RegValue|0x30000, mac, 6);
m2m_memcpy(pu8MacAddr,mac,6);
if(pu8IsValid) *pu8IsValid = 1;
return ret;
_EXIT_ERR:
if(pu8IsValid) *pu8IsValid = 0;
return ret;
}
sint8 nmi_get_mac_address(uint8 *pu8MacAddr)
{
sint8 ret;
uint32 u32RegValue;
uint8 mac[6];
tstrGpRegs strgp = {0};
ret = nm_read_reg_with_ret(rNMI_GP_REG_2, &u32RegValue);
if(ret != M2M_SUCCESS) goto _EXIT_ERR;
#ifdef ARDUINO
if (u32RegValue) {
ret = nm_read_block(u32RegValue|0x30000,(uint8*)&strgp,sizeof(tstrGpRegs));
if(ret != M2M_SUCCESS) goto _EXIT_ERR;
u32RegValue = strgp.u32Mac_efuse_mib;
} else {
// firmware version 19.3.0
ret = nm_read_reg_with_ret(rNMI_GP_REG_0, &u32RegValue);
if(ret != M2M_SUCCESS) goto _EXIT_ERR;
}
#else
ret = nm_read_block(u32RegValue|0x30000,(uint8*)&strgp,sizeof(tstrGpRegs));
if(ret != M2M_SUCCESS) goto _EXIT_ERR;
u32RegValue = strgp.u32Mac_efuse_mib;
#endif
u32RegValue &=0x0000ffff;
ret = nm_read_block(u32RegValue|0x30000, mac, 6);
m2m_memcpy(pu8MacAddr, mac, 6);
return ret;
_EXIT_ERR:
return ret;
}
/**
* @fn spi_flash_read_internal
* @brief Read from data from SPI flash
* @param[OUT] pu8Buf
* Pointer to data buffer
* @param[IN] u32Addr
* Address to read from at the SPI flash
* @param[IN] u32Sz
* Data size
*/
static sint8 spi_flash_read_internal(uint8 *pu8Buf, uint32 u32Addr, uint32 u32Sz)
{
sint8 ret = M2M_SUCCESS;
/* read size must be < 64KB */
ret = spi_flash_load_to_cortus_mem(HOST_SHARE_MEM_BASE, u32Addr, u32Sz);
if(M2M_SUCCESS != ret) goto ERR;
ret = nm_read_block(HOST_SHARE_MEM_BASE, pu8Buf, u32Sz);
ERR:
return ret;
}
sint8 nmi_get_mac_address(uint8 *pu8MacAddr)
{
sint8 ret;
uint32 u32RegValue;
uint8 mac[6];
tstrGpRegs strgp = {0};
ret = nm_read_reg_with_ret(rNMI_GP_REG_0, &u32RegValue);
if(ret != M2M_SUCCESS) goto _EXIT_ERR;
ret = nm_read_block(u32RegValue|0x30000,(uint8*)&strgp,sizeof(tstrGpRegs));
if(ret != M2M_SUCCESS) goto _EXIT_ERR;
u32RegValue = strgp.u32Mac_efuse_mib;
u32RegValue &=0x0000ffff;
ret = nm_read_block(u32RegValue|0x30000, mac, 6);
m2m_memcpy(pu8MacAddr, mac, 6);
return ret;
_EXIT_ERR:
return ret;
}
sint8 nmi_get_mac_address(uint8 *pu8MacAddr)
{
sint8 ret;
uint32 u32RegValue;
uint8 mac[6];
ret = nm_read_reg_with_ret(rNMI_GP_REG_0, &u32RegValue);
if(ret != M2M_SUCCESS) goto _EXIT_ERR;
u32RegValue &=0x0000ffff;
nm_read_block(u32RegValue|0x30000, mac, 6);
m2m_memcpy(pu8MacAddr, mac, 6);
return ret;
_EXIT_ERR:
return ret;
}
/**
* @fn hif_isr
* @brief Host interface interrupt service routine
* @author M. Abdelmawla
* @date 15 July 2012
* @return 1 in case of interrupt received else 0 will be returned
* @version 1.0
*/
static sint8 hif_isr(void)
{
sint8 ret = M2M_SUCCESS;
uint32 reg;
volatile tstrHifHdr strHif;
ret = nm_read_reg_with_ret(WIFI_HOST_RCV_CTRL_0, ®);
if(M2M_SUCCESS == ret)
{
if(reg & 0x1) /* New interrupt has been received */
{
uint16 size;
nm_bsp_interrupt_ctrl(0);
/*Clearing RX interrupt*/
reg &= ~NBIT0;
ret = nm_write_reg(WIFI_HOST_RCV_CTRL_0,reg);
if(ret != M2M_SUCCESS)goto ERR1;
gstrHifCxt.u8HifRXDone = 1;
size = (uint16)((reg >> 2) & 0xfff);
if (size > 0) {
uint32 address = 0;
/**
start bus transfer
**/
ret = nm_read_reg_with_ret(WIFI_HOST_RCV_CTRL_1, &address);
if(M2M_SUCCESS != ret)
{
M2M_ERR("(hif) WIFI_HOST_RCV_CTRL_1 bus fail\n");
nm_bsp_interrupt_ctrl(1);
goto ERR1;
}
gstrHifCxt.u32RxAddr = address;
gstrHifCxt.u32RxSize = size;
ret = nm_read_block(address, (uint8*)&strHif, sizeof(tstrHifHdr));
strHif.u16Length = NM_BSP_B_L_16(strHif.u16Length);
if(M2M_SUCCESS != ret)
{
M2M_ERR("(hif) address bus fail\n");
nm_bsp_interrupt_ctrl(1);
goto ERR1;
}
if(strHif.u16Length != size)
{
if((size - strHif.u16Length) > 4)
{
M2M_ERR("(hif) Corrupted packet Size = %u <L = %u, G = %u, OP = %02X>\n",
size, strHif.u16Length, strHif.u8Gid, strHif.u8Opcode);
nm_bsp_interrupt_ctrl(1);
ret = M2M_ERR_BUS_FAIL;
goto ERR1;
}
}
if(M2M_REQ_GROUP_WIFI == strHif.u8Gid)
{
if(gstrHifCxt.pfWifiCb)
gstrHifCxt.pfWifiCb(strHif.u8Opcode,strHif.u16Length - M2M_HIF_HDR_OFFSET, address + M2M_HIF_HDR_OFFSET);
else
M2M_ERR("WIFI callback is not registered\n");
}
else if(M2M_REQ_GROUP_IP == strHif.u8Gid)
{
if(gstrHifCxt.pfIpCb)
gstrHifCxt.pfIpCb(strHif.u8Opcode,strHif.u16Length - M2M_HIF_HDR_OFFSET, address + M2M_HIF_HDR_OFFSET);
else
M2M_ERR("Scoket callback is not registered\n");
}
else if(M2M_REQ_GROUP_OTA == strHif.u8Gid)
{
if(gstrHifCxt.pfOtaCb)
gstrHifCxt.pfOtaCb(strHif.u8Opcode,strHif.u16Length - M2M_HIF_HDR_OFFSET, address + M2M_HIF_HDR_OFFSET);
else
M2M_ERR("Ota callback is not registered\n");
}
else if(M2M_REQ_GROUP_CRYPTO == strHif.u8Gid)
{
if(gstrHifCxt.pfCryptoCb)
gstrHifCxt.pfCryptoCb(strHif.u8Opcode,strHif.u16Length - M2M_HIF_HDR_OFFSET, address + M2M_HIF_HDR_OFFSET);
else
M2M_ERR("Crypto callback is not registered\n");
}
else if(M2M_REQ_GROUP_SIGMA == strHif.u8Gid)
{
if(gstrHifCxt.pfSigmaCb)
gstrHifCxt.pfSigmaCb(strHif.u8Opcode,strHif.u16Length - M2M_HIF_HDR_OFFSET, address + M2M_HIF_HDR_OFFSET);
else
M2M_ERR("Sigma callback is not registered\n");
}
else if(M2M_REQ_GROUP_SSL == strHif.u8Gid)
{
if(gstrHifCxt.pfSslCb)
gstrHifCxt.pfSslCb(strHif.u8Opcode,strHif.u16Length - M2M_HIF_HDR_OFFSET, address + M2M_HIF_HDR_OFFSET);
}
else
{
M2M_ERR("(hif) invalid group ID\n");
ret = M2M_ERR_BUS_FAIL;
goto ERR1;
}
if(gstrHifCxt.u8HifRXDone)
{
M2M_ERR("(hif) host app didn't set RX Done <%u><%X>\n", strHif.u8Gid, strHif.u8Opcode);
ret = hif_set_rx_done();
if(ret != M2M_SUCCESS) goto ERR1;
}
}
else
{
M2M_ERR("(hif) Wrong Size\n");
ret = M2M_ERR_RCV;
goto ERR1;
}
}
else
{
void BigInt_ModExp
(
uint8 *pu8X, uint16 u16XSize,
uint8 *pu8E, uint16 u16ESize,
uint8 *pu8M, uint16 u16MSize,
uint8 *pu8R, uint16 u16RSize
)
{
uint32 u32Reg;
uint8 au8Tmp[780] = {0};
uint32 u32XAddr = SHARED_MEM_BASE;
uint32 u32MAddr;
uint32 u32EAddr;
uint32 u32RAddr;
uint8 u8EMswBits = 32;
uint32 u32Mprime = 0x7F;
uint16 u16XSizeWords,u16ESizeWords;
uint32 u32Exponent;
u16XSizeWords = (u16XSize + 3) / 4;
u16ESizeWords = (u16ESize + 3) / 4;
u32MAddr = u32XAddr + (u16XSizeWords * 4);
u32EAddr = u32MAddr + (u16XSizeWords * 4);
u32RAddr = u32EAddr + (u16ESizeWords * 4);
/* Reset the core.
*/
u32Reg = 0;
u32Reg |= BIGINT_MISC_CTRL_CTL_RESET;
u32Reg = nm_read_reg(BIGINT_MISC_CTRL);
u32Reg &= ~BIGINT_MISC_CTRL_CTL_RESET;
u32Reg = nm_read_reg(BIGINT_MISC_CTRL);
nm_write_block(u32RAddr,au8Tmp, u16RSize);
/* Write Input Operands to Chip Memory.
*/
/*------- X -------*/
FlipBuffer(pu8X,au8Tmp,u16XSize);
nm_write_block(u32XAddr,au8Tmp,u16XSizeWords * 4);
/*------- E -------*/
m2m_memset(au8Tmp, 0, sizeof(au8Tmp));
FlipBuffer(pu8E, au8Tmp, u16ESize);
nm_write_block(u32EAddr, au8Tmp, u16ESizeWords * 4);
u32Exponent = GET_UINT32(au8Tmp, (u16ESizeWords * 4) - 4);
while((u32Exponent & NBIT31)== 0)
{
u32Exponent <<= 1;
u8EMswBits --;
}
/*------- M -------*/
m2m_memset(au8Tmp, 0, sizeof(au8Tmp));
FlipBuffer(pu8M, au8Tmp, u16XSize);
nm_write_block(u32MAddr, au8Tmp, u16XSizeWords * 4);
/* Program the addresses of the input operands.
*/
nm_write_reg(BIGINT_ADDR_X, u32XAddr);
nm_write_reg(BIGINT_ADDR_E, u32EAddr);
nm_write_reg(BIGINT_ADDR_M, u32MAddr);
nm_write_reg(BIGINT_ADDR_R, u32RAddr);
/* Mprime.
*/
nm_write_reg(BIGINT_M_PRIME,u32Mprime);
/* Length.
*/
u32Reg = (u16XSizeWords & 0xFF);
u32Reg += ((u16ESizeWords & 0xFF) << 8);
u32Reg += (u8EMswBits << 16);
nm_write_reg(BIGINT_LENGTH,u32Reg);
/* CTRL Register.
*/
u32Reg = nm_read_reg(BIGINT_MISC_CTRL);
u32Reg ^= BIGINT_MISC_CTRL_CTL_START;
u32Reg |= BIGINT_MISC_CTRL_CTL_FORCE_BARRETT;
//u32Reg |= BIGINT_MISC_CTRL_CTL_M_PRIME_VALID;
#if ENABLE_FLIPPING == 0
u32Reg |= BIGINT_MISC_CTRL_CTL_MSW_FIRST;
#endif
nm_write_reg(BIGINT_MISC_CTRL,u32Reg);
/* Wait for computation to complete. */
while(1)
{
u32Reg = nm_read_reg(BIGINT_IRQ_STS);
if(u32Reg & BIGINT_IRQ_STS_DONE)
{
break;
}
}
nm_write_reg(BIGINT_IRQ_STS,0);
m2m_memset(au8Tmp, 0, sizeof(au8Tmp));
nm_read_block(u32RAddr, au8Tmp, u16RSize);
FlipBuffer(au8Tmp, pu8R, u16RSize);
}
sint8 m2m_crypto_sha256_hash_finish(tstrM2mSha256Ctxt *pstrSha256Ctxt, uint8 *pu8Sha256Digest)
{
sint8 s8Ret = M2M_ERR_FAIL;
tstrSHA256HashCtxt *pstrSHA256 = (tstrSHA256HashCtxt*)pstrSha256Ctxt;
if(pstrSHA256 != NULL)
{
uint32 u32ReadAddr;
uint32 u32WriteAddr = SHARED_MEM_BASE;
uint32 u32Addr = u32WriteAddr;
uint16 u16Offset;
uint16 u16PaddingLength;
uint16 u16NBlocks = 1;
uint32 u32RegVal = 0;
uint32 u32Idx,u32ByteIdx;
uint32 au32Digest[M2M_SHA256_DIGEST_LEN / 4];
uint8 u8IsDone = 0;
nm_write_reg(SHA256_CTRL,u32RegVal);
u32RegVal |= SHA256_CTRL_FORCE_SHA256_QUIT_MASK;
nm_write_reg(SHA256_CTRL,u32RegVal);
if(pstrSHA256->u8InitHashFlag)
{
pstrSHA256->u8InitHashFlag = 0;
u32RegVal |= SHA256_CTRL_INIT_SHA256_STATE_MASK;
}
/* Calculate the offset of the last data byte in the current block. */
u16Offset = (uint16)(pstrSHA256->u32TotalLength % SHA_BLOCK_SIZE);
/* Add the padding byte 0x80. */
pstrSHA256->au8CurrentBlock[u16Offset ++] = 0x80;
/* Calculate the required padding to complete
one Hash Block Size.
*/
u16PaddingLength = SHA_BLOCK_SIZE - u16Offset;
m2m_memset(&pstrSHA256->au8CurrentBlock[u16Offset], 0, u16PaddingLength);
/* If the padding count is not enough to hold 64-bit representation of
the total input message length, one padding block is required.
*/
if(u16PaddingLength < 8)
{
nm_write_block(u32Addr, pstrSHA256->au8CurrentBlock, SHA_BLOCK_SIZE);
u32Addr += SHA_BLOCK_SIZE;
m2m_memset(pstrSHA256->au8CurrentBlock, 0, SHA_BLOCK_SIZE);
u16NBlocks ++;
}
/* pack the length at the end of the padding block */
PUTU32(pstrSHA256->u32TotalLength << 3, pstrSHA256->au8CurrentBlock, (SHA_BLOCK_SIZE - 4));
u32ReadAddr = u32WriteAddr + (u16NBlocks * SHA_BLOCK_SIZE);
nm_write_block(u32Addr, pstrSHA256->au8CurrentBlock, SHA_BLOCK_SIZE);
nm_write_reg(SHA256_DATA_LENGTH, (u16NBlocks * SHA_BLOCK_SIZE));
nm_write_reg(SHA256_START_RD_ADDR, u32WriteAddr);
nm_write_reg(SHA256_START_WR_ADDR, u32ReadAddr);
u32RegVal |= SHA256_CTRL_START_CALC_MASK;
u32RegVal |= SHA256_CTRL_WR_BACK_HASH_VALUE_MASK;
u32RegVal &= ~(0x7UL << 8);
u32RegVal |= (0x2UL << 8);
nm_write_reg(SHA256_CTRL,u32RegVal);
/* 5. Wait for done_intr */
while(!u8IsDone)
{
u32RegVal = nm_read_reg(SHA256_DONE_INTR_STS);
u8IsDone = u32RegVal & NBIT0;
}
nm_read_block(u32ReadAddr, (uint8*)au32Digest, 32);
/* Convert the output words to an array of bytes.
*/
u32ByteIdx = 0;
for(u32Idx = 0; u32Idx < (M2M_SHA256_DIGEST_LEN / 4); u32Idx ++)
{
pu8Sha256Digest[u32ByteIdx ++] = BYTE_3(au32Digest[u32Idx]);
pu8Sha256Digest[u32ByteIdx ++] = BYTE_2(au32Digest[u32Idx]);
pu8Sha256Digest[u32ByteIdx ++] = BYTE_1(au32Digest[u32Idx]);
pu8Sha256Digest[u32ByteIdx ++] = BYTE_0(au32Digest[u32Idx]);
}
s8Ret = M2M_SUCCESS;
}
return s8Ret;
}
/**
* @fn hif_isr
* @brief Host interface interrupt service routine
* @author M. Abdelmawla
* @date 15 July 2012
* @return 1 in case of interrupt received else 0 will be returned
* @version 1.0
*/
static sint8 hif_isr(void)
{
sint8 ret = M2M_ERR_BUS_FAIL;
uint32 reg;
volatile tstrHifHdr strHif;
ret = hif_chip_wake();
if(ret == M2M_SUCCESS)
{
ret = nm_read_reg_with_ret(WIFI_HOST_RCV_CTRL_0, ®);
if(M2M_SUCCESS == ret)
{
if(reg & 0x1) /* New interrupt has been received */
{
uint16 size;
nm_bsp_interrupt_ctrl(0);
/*Clearing RX interrupt*/
reg &= ~(1<<0);
ret = nm_write_reg(WIFI_HOST_RCV_CTRL_0,reg);
if(ret != M2M_SUCCESS)goto ERR1;
gu8HifSizeDone = 0;
size = (uint16)((reg >> 2) & 0xfff);
if (size > 0) {
uint32 address = 0;
/**
start bus transfer
**/
ret = nm_read_reg_with_ret(WIFI_HOST_RCV_CTRL_1, &address);
if(M2M_SUCCESS != ret)
{
M2M_ERR("(hif) WIFI_HOST_RCV_CTRL_1 bus fail\n");
nm_bsp_interrupt_ctrl(1);
goto ERR1;
}
ret = nm_read_block(address, (uint8*)&strHif, sizeof(tstrHifHdr));
strHif.u16Length = NM_BSP_B_L_16(strHif.u16Length);
if(M2M_SUCCESS != ret)
{
M2M_ERR("(hif) address bus fail\n");
nm_bsp_interrupt_ctrl(1);
goto ERR1;
}
if(strHif.u16Length != size)
{
if((size - strHif.u16Length) > 4)
{
M2M_ERR("(hif) Corrupted packet Size = %u <L = %u, G = %u, OP = %02X>\n",
size, strHif.u16Length, strHif.u8Gid, strHif.u8Opcode);
nm_bsp_interrupt_ctrl(1);
ret = M2M_ERR_BUS_FAIL;
goto ERR1;
}
}
if(M2M_REQ_GROUP_WIFI == strHif.u8Gid)
{
if(pfWifiCb)
pfWifiCb(strHif.u8Opcode,strHif.u16Length - M2M_HIF_HDR_OFFSET, address + M2M_HIF_HDR_OFFSET);
}
else if(M2M_REQ_GROUP_IP == strHif.u8Gid)
{
if(pfIpCb)
pfIpCb(strHif.u8Opcode,strHif.u16Length - M2M_HIF_HDR_OFFSET, address + M2M_HIF_HDR_OFFSET);
}
else if(M2M_REQ_GROUP_OTA == strHif.u8Gid)
{
if(pfOtaCb)
pfOtaCb(strHif.u8Opcode,strHif.u16Length - M2M_HIF_HDR_OFFSET, address + M2M_HIF_HDR_OFFSET);
}
else if(M2M_REQ_GROUP_CRYPTO == strHif.u8Gid)
{
if(pfCryptoCb)
pfCryptoCb(strHif.u8Opcode,strHif.u16Length - M2M_HIF_HDR_OFFSET, address + M2M_HIF_HDR_OFFSET);
}
else if(M2M_REQ_GROUP_SIGMA == strHif.u8Gid)
{
if(pfSigmaCb)
pfSigmaCb(strHif.u8Opcode,strHif.u16Length - M2M_HIF_HDR_OFFSET, address + M2M_HIF_HDR_OFFSET);
}
else
{
M2M_ERR("(hif) invalid group ID\n");
ret = M2M_ERR_BUS_FAIL;
goto ERR1;
}
#ifndef ENABLE_UNO_BOARD
if(!gu8HifSizeDone)
{
M2M_ERR("(hif) host app didn't set RX Done\n");
ret = hif_set_rx_done();
}
#endif
}
else
{
ret = M2M_ERR_RCV;
M2M_ERR("(hif) Wrong Size\n");
goto ERR1;
}
}
else
{
