/*
* dev_c3660_iofpga_access()
*/
static void *
dev_c3660_iofpga_access(cpu_gen_t *cpu,struct vdevice *dev,
m_uint32_t offset,u_int op_size,u_int op_type,
m_uint64_t *data)
{
struct c3600_iofpga_data *d = dev->priv_data;
u_int slot;
if (op_type == MTS_READ)
*data = 0x0;
#if DEBUG_ACCESS
if (offset != 0x0c) {
if (op_type == MTS_READ) {
cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n",
offset,cpu_get_pc(cpu),op_size);
} else {
cpu_log(cpu,"IO_FPGA",
"writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n",
offset,cpu_get_pc(cpu),*data,op_size);
}
}
#endif
switch(offset) {
/*
* 0x7d00 is written here regularly.
* Some kind of hardware watchdog ?
*/
case 0x0000c:
break;
/* Probably flash protection (if 0, no write access allowed) */
case 0x00008:
if (op_type == MTS_READ)
*data = 0xFF;
break;
/* Bootflash of 8 Mb */
case 0x0000a:
if (op_type == MTS_READ)
*data = 0x1000;
break;
/* NM presence - slots 1 to 4 */
case 0x10006:
if (op_type == MTS_READ)
*data = nm_get_status_2(d,0);
break;
/* NM presence - slot 5 to 6 */
case 0x10008:
if (op_type == MTS_READ)
*data = nm_get_status_2(d,1);
break;
/* Fan status, PS presence */
case 0x10018:
if (op_type == MTS_READ)
*data = 0x0000;
break;
/* unknown, read by env monitor */
case 0x1001a:
if (op_type == MTS_READ)
*data = 0x0000;
break;
/* board temperature */
case 0x30004:
if (op_type == MTS_READ) {
*data = 32 + 1;
}
break;
/* sh c3600: Per Slot Intr Mask */
case 0x10016:
if (op_type == MTS_READ)
*data = 0x12;
break;
/* sh c3600: OIR fsm state slot's (12) */
case 0x10020:
if (op_type == MTS_READ)
*data = 0x00;
break;
/* sh c3600: OIR fsm state slot's (34) */
case 0x10022:
if (op_type == MTS_READ)
*data = 0x00;
break;
/* sh c3600: OIR fsm state slot's (56) */
case 0x10024:
if (op_type == MTS_READ)
*data = 0x00;
break;
/*
* Backplane EEPROM.
*
* Bit 7: 0=Telco chassis, 1=Enterprise chassis.
*/
case 0x10000:
if (op_type == MTS_WRITE)
nmc93cX6_write(&d->router->mb_eeprom_group,(u_int)(*data));
else
*data = nmc93cX6_read(&d->router->mb_eeprom_group) | 0x80;
break;
/* NM EEPROMs - slots 1 to 6 */
case 0x1000a:
case 0x1000b:
case 0x1000c:
case 0x1000d:
case 0x1000e:
case 0x1000f:
slot = (offset - 0x1000a) + 1;
if (op_type == MTS_WRITE) {
nmc93cX6_write(&d->router->c3660_nm_eeprom_group[slot],
(u_int)(*data));
} else {
*data = nmc93cX6_read(&d->router->c3660_nm_eeprom_group[slot]);
}
break;
/* NM EEPROM - slot 0 */
case 0x20006:
if (op_type == MTS_WRITE) {
nmc93cX6_write(&d->router->c3660_nm_eeprom_group[0],
(u_int)(*data));
} else {
*data = nmc93cX6_read(&d->router->c3660_nm_eeprom_group[0]);
}
break;
/* Unknown EEPROMs ? */
case 0x20000:
case 0x20002:
case 0x20004:
if (op_type == MTS_READ)
*data = 0xFFFF;
break;
/* IO Mask (displayed by "show c3600") */
case 0x20008:
if (op_type == MTS_READ)
*data = d->io_mask;
else
d->io_mask = *data;
break;
/* 0: 3640, 4 << 5: 3620, 3 << 5: 3660 */
case 0x30000:
if (op_type == MTS_READ)
*data = 3 << 5;
break;
/* ??? */
case 0x30008:
if (op_type == MTS_READ)
*data = 0xFF;
break;
/*
* Read at net interrupt (size 4).
* It seems that there are 4 lines per slot.
*
* Bit 24-27: slot 1
* Bit 16-19: slot 2
* Bit 28-31: slot 3
* Bit 20-23: slot 4
* Bit 08-11: slot 5
* Bit 00-03: slot 6
*
* Other bits are unknown.
*/
case 0x10010:
if (op_type == MTS_READ)
*data = d->net_irq_status[0];
break;
/*
* Read at net interrupt (size 1)
*
* Bit 7-6: we get "Unexpected AIM interrupt on AIM slot 1".
* Bit 5-4: we get "Unexpected AIM interrupt on AIM slot 0".
* Bit 0-3: net interrupt for slot 0.
*/
case 0x20010:
if (op_type == MTS_READ)
*data = d->net_irq_status[1];
break;
/*
* Read when a PA Management interrupt is triggered.
*
* If not 0, we get:
* "Error: Unexpected NM Interrupt received from slot: x"
*/
case 0x10014:
if (op_type == MTS_READ)
*data = 0x00;
vm_clear_irq(d->router->vm,C3600_NM_MGMT_IRQ);
break;
/*
* Read when an external interrupt is triggered.
*
* Bit 4: 1 = %UNKNOWN-1-GT64010: Unknown fatal interrupt(s)
* Bit 6: 1 = %OIRINT: OIR Event has occurred oir_ctrl 1000 oir_stat FFFF
*
* oir_ctrl = register 0x10004
* oir_stat = register 0x10006
*/
case 0x2000a:
if (op_type == MTS_READ)
*data = 0x54;
vm_clear_irq(d->router->vm,C3600_EXT_IRQ);
break;
#if DEBUG_UNKNOWN
default:
if (op_type == MTS_READ) {
cpu_log(cpu,"IO_FPGA",
"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n",
offset,cpu_get_pc(cpu),op_size);
} else {
cpu_log(cpu,"IO_FPGA",
"write to unknown addr 0x%x, value=0x%llx, "
"pc=0x%llx (size=%u)\n",
offset,*data,cpu_get_pc(cpu),op_size);
}
#endif
}
return NULL;
}
/*
* dev_c2600_iofpga_access()
*/
static void *
dev_c2600_iofpga_access(cpu_gen_t *cpu,struct vdevice *dev,
m_uint32_t offset,u_int op_size,u_int op_type,
m_uint64_t *data)
{
struct c2600_iofpga_data *d = dev->priv_data;
if (op_type == MTS_READ)
*data = 0x0;
#if DEBUG_ACCESS
if (op_type == MTS_READ) {
cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n",
offset,cpu_get_pc(cpu),op_size);
} else {
cpu_log(cpu,"IO_FPGA",
"writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n",
offset,cpu_get_pc(cpu),*data,op_size);
}
#endif
switch(offset) {
case 0x04:
if (op_type == MTS_READ)
*data = 0x00;
break;
/*
* Network Interrupt.
*
* Bit 0-3: slot 1.
* Bit 4: slot 0 (MB), port 0
* Bit 5: slot 0 (MB), port 1
* Other: AIM ? (error messages displayed)
*/
case 0x08:
if (op_type == MTS_READ)
*data = d->net_irq_status;
break;
case 0x10:
if (op_type == MTS_READ)
*data = d->wic_select;
else {
d->wic_select = *data;
}
break;
case 0x14:
if (op_type == MTS_READ)
*data = 0; //0xFFFFFFFF;
break;
/*
* Flash Related: 0x1y
*
* Bit 1: card present in slot 0 / WIC 0.
* Bit 2: card present in slot 0 / WIC 1.
*
* Other bits unknown.
*/
case 0x0c:
if (op_type == MTS_READ) {
*data = 0x10;
/* check WIC 0 */
if (vm_slot_check_eeprom(d->router->vm,0,0x10))
*data |= 0x02;
/* check WIC 1 */
if (vm_slot_check_eeprom(d->router->vm,0,0x20))
*data |= 0x04;
}
break;
/* NM EEPROM */
case 0x1c:
if (op_type == MTS_WRITE)
nmc93cX6_write(&d->router->nm_eeprom_group,(u_int)(*data));
else
*data = nmc93cX6_read(&d->router->nm_eeprom_group);
break;
#if DEBUG_UNKNOWN
default:
if (op_type == MTS_READ) {
cpu_log(cpu,"IO_FPGA",
"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n",
offset,cpu_get_pc(cpu),op_size);
} else {
cpu_log(cpu,"IO_FPGA",
"write to unknown addr 0x%x, value=0x%llx, "
"pc=0x%llx (size=%u)\n",
offset,*data,cpu_get_pc(cpu),op_size);
}
#endif
}
return NULL;
}
/*
* dev_c3620_c3640_iofpga_access()
*/
static void *
dev_c3620_c3640_iofpga_access(cpu_gen_t *cpu,struct vdevice *dev,
m_uint32_t offset,u_int op_size,u_int op_type,
m_uint64_t *data)
{
struct c3600_iofpga_data *d = dev->priv_data;
if (op_type == MTS_READ)
*data = 0x0;
#if DEBUG_ACCESS
if (offset != 0x0c) {
if (op_type == MTS_READ) {
cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n",
offset,cpu_get_pc(cpu),op_size);
} else {
cpu_log(cpu,"IO_FPGA",
"writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n",
offset,cpu_get_pc(cpu),*data,op_size);
}
}
#endif
switch(offset) {
/* Probably flash protection (if 0, no write access allowed) */
case 0x00008:
if (op_type == MTS_READ)
*data = 0xFF;
break;
/* Bootflash of 8 Mb */
case 0x0000a:
if (op_type == MTS_READ)
*data = 0x1000;
break;
/*
* 0x7d00 is written here regularly.
* Some kind of hardware watchdog ?
*/
case 0x0000c:
break;
/* Mainboard EEPROM */
case 0x0000e:
if (op_type == MTS_WRITE)
nmc93cX6_write(&d->router->mb_eeprom_group,(u_int)(*data));
else
*data = nmc93cX6_read(&d->router->mb_eeprom_group);
break;
case 0x10004: /* ??? OIR control ??? */
if (op_type == MTS_READ) {
*data = 0x0000;
}
break;
/*
* Network modules presence.
*
* Bit 0: 0 = NM in slot 0 is valid
* Bit 1: 0 = NM in slot 1 is valid
* Bit 2: 0 = NM in slot 2 is valid
* Bit 3: 0 = NM in slot 3 is valid
*
* Very well explained on Cisco website:
* http://www.cisco.com/en/US/customer/products/hw/routers/ps274/products_tech_note09186a0080109510.shtml
*/
case 0x10006:
if (op_type == MTS_READ)
*data = nm_get_status_1(d);
break;
/*
* NM EEPROMs.
*/
case 0x10008:
if (op_type == MTS_WRITE) {
d->eeprom_slot = *data & 0x03;
nm_eeprom_select(d,d->eeprom_slot);
nmc93cX6_write(&d->router->nm_eeprom_group,*data);
} else {
*data = nmc93cX6_read(&d->router->nm_eeprom_group);
}
break;
/* Network interrupt status */
case 0x20000: /* slot 1 */
if (op_type == MTS_READ)
*data = d->net_irq_status[0] >> 24;
break;
case 0x20001: /* slot 0 */
if (op_type == MTS_READ)
*data = d->net_irq_status[0] >> 16;
break;
case 0x20002: /* slot 3 */
if (op_type == MTS_READ)
*data = d->net_irq_status[0] >> 8;
break;
case 0x20003: /* slot 2 */
if (op_type == MTS_READ)
*data = d->net_irq_status[0];
break;
/*
* Read when a PA Management interrupt is triggered.
*
* If not 0, we get:
* "Error: Unexpected NM Interrupt received from slot: x"
*/
case 0x20004:
if (op_type == MTS_READ)
*data = 0x00;
vm_clear_irq(d->router->vm,C3600_NM_MGMT_IRQ);
break;
/*
* Read when an external interrupt is triggered.
*
* Bit 4: 1 = %UNKNOWN-1-GT64010: Unknown fatal interrupt(s)
* Bit 6: 1 = %OIRINT: OIR Event has occurred oir_ctrl 1000 oir_stat FFFF
*
* oir_ctrl = register 0x10004
* oir_stat = register 0x10006
*/
case 0x20006:
if (op_type == MTS_READ)
*data = 0x00;
vm_clear_irq(d->router->vm,C3600_EXT_IRQ);
break;
/* IO Mask (displayed by "show c3600") */
case 0x20008:
if (op_type == MTS_READ)
*data = d->io_mask;
else
d->io_mask = *data;
break;
/*
* Platform type ?
* 0: 3640, 4 << 5: 3620, 3 << 5: 3660
*/
case 0x30000:
if (op_type == MTS_READ) {
switch(c3600_chassis_get_id(d->router)) {
case 3620:
*data = 4 << 5;
break;
case 3640:
*data = 0 << 5;
break;
case 3660:
*data = 3 << 5;
break;
default:
*data = 0;
}
}
break;
/* ??? */
case 0x30002:
if (op_type == MTS_WRITE) {
d->sel = *data;
} else {
//*data = d->sel;
}
break;
/*
* Environmental parameters, determined with "sh env all".
*
* Bit 0: 0 = overtemperature condition.
* Bit 4: 0 = RPS present.
* Bit 5: 0 = Input Voltage status failure.
* Bit 6: 1 = Thermal status failure.
* Bit 7: 1 = DC Output Voltage status failure.
*/
case 0x30004:
if (op_type == MTS_READ) {
*data = 32 + 1;
}
break;
#if DEBUG_UNKNOWN
default:
if (op_type == MTS_READ) {
cpu_log(cpu,"IO_FPGA",
"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n",
offset,cpu_get_pc(cpu),op_size);
} else {
cpu_log(cpu,"IO_FPGA",
"write to unknown addr 0x%x, value=0x%llx, "
"pc=0x%llx (size=%u)\n",
offset,*data,cpu_get_pc(cpu),op_size);
}
#endif
}
return NULL;
}
