/**
* @brief Deactivates the USB peripheral.
*
* @param[in] usbp pointer to the @p USBDriver object
*
* @notapi
*/
void usb_lld_stop(USBDriver *usbp) {
stm32_otg_t *otgp = usbp->otg;
/* If in ready state then disables the USB clock.*/
if (usbp->state != USB_STOP) {
/* Disabling all endpoints in case the driver has been stopped while
active.*/
otg_disable_ep(usbp);
usbp->txpending = 0;
otgp->DAINTMSK = 0;
otgp->GAHBCFG = 0;
otgp->GCCFG = 0;
#if STM32_USB_USE_USB1
if (&USBD1 == usbp) {
nvicDisableVector(STM32_OTG1_NUMBER);
rccDisableOTG1(FALSE);
}
#endif
#if STM32_USB_USE_USB2
if (&USBD2 == usbp) {
nvicDisableVector(STM32_OTG2_NUMBER);
rccDisableOTG2(FALSE);
}
#endif
}
}
/**
* @brief Deactivates the GPT peripheral.
*
* @param[in] gptp pointer to the @p GPTDriver object
*
* @notapi
*/
void gpt_lld_stop(GPTDriver *gptp) {
if (gptp->state == GPT_READY) {
SIM->SCGC6 &= ~SIM_SCGC6_PIT;
/* Disable the channel */
gptp->channel->TCTRL = 0;
/* Clear pending interrupts */
gptp->channel->TFLG |= PIT_TFLG_TIF;
#if KINETIS_GPT_USE_PIT0
if (&GPTD1 == gptp) {
nvicDisableVector(PITChannel0_IRQn);
}
#endif
#if KINETIS_GPT_USE_PIT1
if (&GPTD2 == gptp) {
nvicDisableVector(PITChannel1_IRQn);
}
#endif
#if KINETIS_GPT_USE_PIT2
if (&GPTD3 == gptp) {
nvicDisableVector(PITChannel2_IRQn);
}
#endif
#if KINETIS_GPT_USE_PIT3
if (&GPTD4 == gptp) {
nvicDisableVector(PITChannel4_IRQn);
}
#endif
}
}
/**
* @brief Low level serial driver stop.
* @details De-initializes the UART, stops the associated clock, resets the
* interrupt vector.
*
* @param[in] sdp pointer to a @p SerialDriver object
*
* @notapi
*/
void sd_lld_stop( SerialDriver *sdp ) {
if (sdp->state == SD_READY) {
sdp->uart->INTENCLR = STAT_TXRDY | STAT_RXRDY;
sdp->uart->CFG = 0;
#if LPC8xx_SERIAL_USE_UART0
if (&SD1 == sdp) {
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1<<12);
nvicDisableVector(UART0_IRQn);
return;
}
#endif
#if LPC8xx_SERIAL_USE_UART1
if (&SD2 == sdp) {
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1<<13);
nvicDisableVector(UART1_IRQn);
return;
}
#endif
#if LPC8xx_SERIAL_USE_UART2
if (&SD3 == sdp) {
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1<<14);
nvicDisableVector(UART2_IRQn);
return;
}
#endif
}
}
/**
* @brief Deactivates the CAN peripheral.
*
* @param[in] canp pointer to the @p CANDriver object
*
* @notapi
*/
void can_lld_stop(CANDriver *canp) {
/* If in ready state then disables the CAN peripheral.*/
if (canp->state == CAN_READY) {
canp->can->MOD = CANMOD_RM; /* Reset mode. */
canp->can->IER = 0;
#if (LPC17xx_CAN_USE_CAN1 && LPC17xx_CAN_USE_CAN2) == 0
nvicDisableVector(CAN_IRQn); /* Interrupt disabled only if one CAN is in use. */
#endif
#if LPC17xx_CAN_USE_CAN1
if (&CAND1 == canp) {
LPC_SC->PCONP &= ~(1UL << 13);
}
#endif
#if LPC17xx_CAN_USE_CAN2
if (&CAND2 == canp) {
LPC_SC->PCONP &= ~(1UL << 14);
}
#endif
#if CAN_USE_SLEEP_MODE
nvicDisableVector(CANActivity_IRQn);
#endif /* CAN_USE_SLEEP_MODE */
}
}
/**
* @brief Deactivates the SPI peripheral.
*
* @param[in] spip pointer to the @p SPIDriver object
*
* @notapi
*/
void spi_lld_stop(SPIDriver *spip)
{
if (spip->state != SPI_STOP) {
spip->ssi->CR1 = 0;
spip->ssi->CR0 = 0;
spip->ssi->CPSR = 0;
udmaChannelRelease(spip->dmarxnr);
udmaChannelRelease(spip->dmatxnr);
#if TIVA_SPI_USE_SSI0
if (&SPID1 == spip) {
nvicDisableVector(TIVA_SSI0_NUMBER);
}
#endif
#if TIVA_SPI_USE_SSI1
if (&SPID2 == spip) {
nvicDisableVector(TIVA_SSI1_NUMBER);
}
#endif
#if TIVA_SPI_USE_SSI2
if (&SPID3 == spip) {
nvicDisableVector(TIVA_SSI2_NUMBER);
}
#endif
#if TIVA_SPI_USE_SSI3
if (&SPID4 == spip) {
nvicDisableVector(TIVA_SSI3_NUMBER);
}
#endif
}
}
/**
* @brief Deactivates the PWM peripheral.
*
* @param[in] pwmp pointer to a @p PWMDriver object
*
* @notapi
*/
void pwm_lld_stop(PWMDriver *pwmp) {
/* If in ready state then disables the PWM clock.*/
if (pwmp->state == PWM_READY) {
pwmp->tim->TCR = 0; /* Timer disabled. */
pwmp->tim->MCR = 0; /* All IRQs disabled. */
pwmp->tim->IR = 0xFF; /* Clear eventual pending IRQs. */
pwmp->tim->PWMC = 0; /* PWM outputs disable */
#if LPC122x_PWM_USE_CT16B0
if (&PWMD1 == pwmp) {
nvicDisableVector(TIMER_16_0_IRQn);
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 7);
}
#endif
#if LPC122x_PWM_USE_CT16B1
if (&PWMD2 == pwmp) {
nvicDisableVector(TIMER_16_1_IRQn);
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 8);
}
#endif
#if LPC122x_PWM_USE_CT32B0
if (&PWMD3 == pwmp) {
nvicDisableVector(TIMER_32_0_IRQn);
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 9);
}
#endif
#if LPC122x_PWM_USE_CT32B1
if (&PWMD4 == pwmp) {
nvicDisableVector(TIMER_32_1_IRQn);
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 10);
}
#endif
}
}
/**
* @brief Releases a DMA stream.
* @details The stream is freed and, if required, the DMA clock disabled.
* Trying to release a unallocated stream is an illegal operation
* and is trapped if assertions are enabled.
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post The stream is again available.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
*
* @special
*/
void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
chDbgCheck(dmastp != NULL, "dmaStreamRelease");
/* Check if the streams is not taken.*/
chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
"dmaStreamRelease(), #1", "not allocated");
/* Marks the stream as not allocated.*/
dma_streams_mask &= ~(1 << dmastp->selfindex);
/* Disables the associated IRQ vector.*/
#if !(STM32_HAS_DMA2 && !defined(STM32F10X_CL))
nvicDisableVector(dmastp->vector);
#else
/* Check unless it is 10 or 11 stream. If yes, make additional check before
disabling IRQ.*/
if (dmastp->selfindex < 10)
nvicDisableVector(dmastp->vector);
else {
if ((dma_streams_mask & (3 << 10)) == 0)
nvicDisableVector(dmastp->vector);
}
#endif /* STM32_HAS_DMA2 && !STM32F10X_CL */
/* Shutting down clocks that are no more required, if any.*/
if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
rccDisableDMA1(FALSE);
#if STM32_HAS_DMA2
if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0)
rccDisableDMA2(FALSE);
#endif
}
/**
* @brief Deactivates the UART peripheral.
*
* @param[in] uartp pointer to the @p UARTDriver object
*
* @notapi
*/
void uart_lld_stop(UARTDriver *uartp) {
if (uartp->state == UART_READY) {
usart_stop(uartp);
dmaStreamRelease(uartp->dmarx);
dmaStreamRelease(uartp->dmatx);
#if STM32_UART_USE_USART1
if (&UARTD1 == uartp) {
nvicDisableVector(STM32_USART1_NUMBER);
rccDisableUSART1(FALSE);
return;
}
#endif
#if STM32_UART_USE_USART2
if (&UARTD2 == uartp) {
nvicDisableVector(STM32_USART2_NUMBER);
rccDisableUSART2(FALSE);
return;
}
#endif
#if STM32_UART_USE_USART3
if (&UARTD3 == uartp) {
nvicDisableVector(STM32_USART3_NUMBER);
rccDisableUSART3(FALSE);
return;
}
#endif
}
}
/**
* @brief Deactivates the PWM peripheral.
*
* @param[in] pwmp pointer to a @p PWMDriver object
*
* @notapi
*/
void pwm_lld_stop(PWMDriver *pwmp) {
/* If in ready state then disables the PWM clock.*/
if (pwmp->state == PWM_READY) {
#if KINETIS_PWM_USE_TPM0
if (&PWMD1 == pwmp) {
SIM->SCGC6 &= ~SIM_SCGC6_TPM0;
nvicDisableVector(TPM0_IRQn);
}
#endif
#if KINETIS_PWM_USE_TPM1
if (&PWMD2 == pwmp) {
SIM->SCGC6 &= ~SIM_SCGC6_TPM1;
nvicDisableVector(TPM1_IRQn);
}
#endif
#if KINETIS_PWM_USE_TPM2
if (&PWMD3 == pwmp) {
SIM->SCGC6 &= ~SIM_SCGC6_TPM2;
nvicDisableVector(TPM2_IRQn);
}
#endif
/* Disable LPTPM counter.*/
pwmp->tpm->SC = 0;
pwmp->tpm->MOD = 0;
}
}
/**
* @brief Low level serial driver stop.
* @details De-initializes the USART, stops the associated clock, resets the
* interrupt vector.
*
* @param[in] sdp pointer to a @p SerialDriver object
*
* @notapi
*/
void sd_lld_stop(SerialDriver *sdp) {
if (sdp->state == SD_READY) {
/* TODO: Resets the peripheral.*/
#if KINETIS_SERIAL_USE_UART0
if (sdp == &SD1) {
nvicDisableVector(UART0Status_IRQn);
SIM->SCGC4 &= ~SIM_SCGC4_UART0;
}
#endif
#if KINETIS_SERIAL_USE_UART1
if (sdp == &SD2) {
nvicDisableVector(UART1Status_IRQn);
SIM->SCGC4 &= ~SIM_SCGC4_UART1;
}
#endif
#if KINETIS_SERIAL_USE_UART2
if (sdp == &SD3) {
nvicDisableVector(UART2Status_IRQn);
SIM->SCGC4 &= ~SIM_SCGC4_UART2;
}
#endif
}
}
/**
* @brief Deactivates the GPT peripheral.
*
* @param[in] gptp pointer to the @p GPTDriver object
*
* @notapi
*/
void gpt_lld_stop(GPTDriver *gptp) {
if (gptp->state == GPT_READY) {
gptp->tmr->MCR = 0;
gptp->tmr->TCR = 0;
#if LPC11xx_GPT_USE_CT16B0
if (&GPTD1 == gptp) {
nvicDisableVector(TIMER_16_0_IRQn);
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 7);
}
#endif
#if LPC11xx_GPT_USE_CT16B1
if (&GPTD2 == gptp) {
nvicDisableVector(TIMER_16_1_IRQn);
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 8);
}
#endif
#if LPC11xx_GPT_USE_CT32B0
if (&GPTD3 == gptp) {
nvicDisableVector(TIMER_32_0_IRQn);
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 9);
}
#endif
#if LPC11xx_GPT_USE_CT32B1
if (&GPTD4 == gptp) {
nvicDisableVector(TIMER_32_1_IRQn);
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 10);
}
#endif
}
}
/**
* @brief Disables IRQ sources.
*
* @notapi
*/
void irqDeinit(void) {
#if HAL_USE_PAL
nvicDisableVector(EXTI0_1_IRQn);
nvicDisableVector(EXTI2_3_IRQn);
nvicDisableVector(EXTI4_15_IRQn);
#endif
}
/**
* @brief Deactivates the USB peripheral.
*
* @param[in] usbp pointer to the @p USBDriver object
*
* @notapi
*/
void usb_lld_stop(USBDriver *usbp) {
/* If in ready state then disables the USB clock.*/
if (usbp->state == USB_STOP) {
#if STM32_USB_USE_USB1
if (&USBD1 == usbp) {
nvicDisableVector(STM32_USB1_HP_NUMBER);
nvicDisableVector(STM32_USB1_LP_NUMBER);
STM32_USB->CNTR = CNTR_PDWN | CNTR_FRES;
rccDisableUSB(FALSE);
}
#endif
}
}
/**
* @brief Deactivates the ICU peripheral.
*
* @param[in] icup pointer to the @p ICUDriver object
*
* @notapi
*/
void icu_lld_stop(ICUDriver *icup) {
if (icup->state == ICU_READY) {
/* Clock deactivation.*/
icup->tim->CR1 = 0; /* Timer disabled. */
icup->tim->DIER = 0; /* All IRQs disabled. */
icup->tim->SR = 0; /* Clear eventual pending IRQs. */
#if STM32_ICU_USE_TIM1
if (&ICUD1 == icup) {
nvicDisableVector(STM32_TIM1_UP_NUMBER);
nvicDisableVector(STM32_TIM1_CC_NUMBER);
rccDisableTIM1(FALSE);
}
#endif
#if STM32_ICU_USE_TIM2
if (&ICUD2 == icup) {
nvicDisableVector(STM32_TIM2_NUMBER);
rccDisableTIM2(FALSE);
}
#endif
#if STM32_ICU_USE_TIM3
if (&ICUD3 == icup) {
nvicDisableVector(STM32_TIM3_NUMBER);
rccDisableTIM3(FALSE);
}
#endif
#if STM32_ICU_USE_TIM4
if (&ICUD4 == icup) {
nvicDisableVector(STM32_TIM4_NUMBER);
rccDisableTIM4(FALSE);
}
#endif
#if STM32_ICU_USE_TIM5
if (&ICUD5 == icup) {
nvicDisableVector(STM32_TIM5_NUMBER);
rccDisableTIM5(FALSE);
}
#endif
#if STM32_ICU_USE_TIM8
if (&ICUD8 == icup) {
nvicDisableVector(STM32_TIM8_UP_NUMBER);
nvicDisableVector(STM32_TIM8_CC_NUMBER);
rccDisableTIM8(FALSE);
}
#endif
#if STM32_ICU_USE_TIM9
if (&ICUD9 == icup) {
nvicDisableVector(STM32_TIM9_NUMBER);
rccDisableTIM9(FALSE);
}
#endif
}
}
/**
* @brief Deactivates the TIMCAP peripheral.
*
* @param[in] timcapp pointer to the @p TIMCAPDriver object
*
* @notapi
*/
void timcap_lld_stop(TIMCAPDriver *timcapp) {
if (timcapp->state == TIMCAP_READY) {
/* Clock deactivation.*/
timcapp->tim->CR1 = 0; /* Timer disabled. */
timcapp->tim->DIER = 0; /* All IRQs disabled. */
timcapp->tim->SR = 0; /* Clear eventual pending IRQs. */
#if STM32_TIMCAP_USE_TIM1
if (&TIMCAPD1 == timcapp) {
nvicDisableVector(STM32_TIM1_UP_NUMBER);
nvicDisableVector(STM32_TIM1_CC_NUMBER);
rccDisableTIM1(FALSE);
}
#endif
#if STM32_TIMCAP_USE_TIM2
if (&TIMCAPD2 == timcapp) {
nvicDisableVector(STM32_TIM2_NUMBER);
rccDisableTIM2(FALSE);
}
#endif
#if STM32_TIMCAP_USE_TIM3
if (&TIMCAPD3 == timcapp) {
nvicDisableVector(STM32_TIM3_NUMBER);
rccDisableTIM3(FALSE);
}
#endif
#if STM32_TIMCAP_USE_TIM4
if (&TIMCAPD4 == timcapp) {
nvicDisableVector(STM32_TIM4_NUMBER);
rccDisableTIM4(FALSE);
}
#endif
#if STM32_TIMCAP_USE_TIM5
if (&TIMCAPD5 == timcapp) {
nvicDisableVector(STM32_TIM5_NUMBER);
rccDisableTIM5(FALSE);
}
#endif
#if STM32_TIMCAP_USE_TIM8
if (&TIMCAPD8 == timcapp) {
nvicDisableVector(STM32_TIM8_UP_NUMBER);
nvicDisableVector(STM32_TIM8_CC_NUMBER);
rccDisableTIM8(FALSE);
}
#endif
#if STM32_TIMCAP_USE_TIM9
if (&TIMCAPD9 == timcapp) {
nvicDisableVector(STM32_TIM9_NUMBER);
rccDisableTIM9(FALSE);
}
#endif
}
}
/** Disable USART TX DMA.
* \param s The USART DMA state structure.
*/
void usart_tx_dma_disable(usart_tx_dma_state* s)
{
/* Disable DMA stream interrupts with the NVIC. */
if (s->dma == DMA1)
nvicDisableVector(dma_irq_lookup[0][s->stream]);
else if (s->dma == DMA2)
nvicDisableVector(dma_irq_lookup[1][s->stream]);
/* Disable DMA stream. */
DMA_SCR(s->dma, s->stream) &= ~DMA_SxCR_EN;
while (DMA_SCR(s->dma, s->stream) & DMA_SxCR_EN) ;
/* Disable RX DMA on the USART. */
usart_disable_tx_dma(s->usart);
}
void gpdrive_deinit(void) {
if (!m_init_done) {
return;
}
m_init_done = false;
timer_thd_stop = true;
while (timer_thd_stop) {
chThdSleepMilliseconds(1);
}
TIM_DeInit(TIM1);
TIM_DeInit(TIM12);
ADC_DeInit();
DMA_DeInit(DMA2_Stream4);
nvicDisableVector(ADC_IRQn);
dmaStreamRelease(STM32_DMA_STREAM(STM32_DMA_STREAM_ID(2, 4)));
// Restore pins
palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) |
PAL_STM32_OSPEED_HIGHEST |
PAL_STM32_PUDR_FLOATING);
palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) |
PAL_STM32_OSPEED_HIGHEST |
PAL_STM32_PUDR_FLOATING);
}
/**
* @brief Releases a DMA stream.
* @details The stream is freed and, if required, the DMA clock disabled.
* Trying to release a unallocated stream is an illegal operation
* and is trapped if assertions are enabled.
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post The stream is again available.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
*
* @special
*/
void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
osalDbgCheck(dmastp != NULL);
/* Check if the streams is not taken.*/
osalDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0U,
"not allocated");
/* Marks the stream as not allocated.*/
dma_streams_mask &= ~(1U << dmastp->selfindex);
/* Disables the associated IRQ vector if it is no more in use.*/
if ((dma_streams_mask & dmastp->cmask) == 0U) {
nvicDisableVector(dmastp->vector);
}
/* Removes the DMA handler.*/
dma_isr_redir[dmastp->selfindex].dma_func = NULL;
dma_isr_redir[dmastp->selfindex].dma_param = NULL;
/* Shutting down clocks that are no more required, if any.*/
if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0U) {
rccDisableDMA1(false);
}
#if STM32_DMA2_NUM_CHANNELS > 0
if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0U) {
rccDisableDMA2(false);
}
#endif
}
/**
* @brief Deactivates the GPT peripheral.
*
* @param[in] gptp pointer to the @p GPTDriver object
*
* @notapi
*/
void gpt_lld_stop(GPTDriver *gptp) {
gptp->channel->TC_CCR = TC_CCR_CLKDIS;
gptp->channel->TC_IDR = 0xFFFFFFFF;
pmc_disable_peripheral_clock(gptp->peripheral_id);
nvicDisableVector(gptp->irq_id);
}
void encoder_deinit(void) {
nvicDisableVector(HW_ENC_EXTI_CH);
nvicDisableVector(HW_ENC_TIM_ISR_CH);
TIM_DeInit(HW_ENC_TIM);
palSetPadMode(SPI_SW_MISO_GPIO, SPI_SW_MISO_PIN, PAL_MODE_INPUT_PULLUP);
palSetPadMode(SPI_SW_SCK_GPIO, SPI_SW_SCK_PIN, PAL_MODE_INPUT_PULLUP);
palSetPadMode(SPI_SW_CS_GPIO, SPI_SW_CS_PIN, PAL_MODE_INPUT_PULLUP);
palSetPadMode(HW_HALL_ENC_GPIO1, HW_HALL_ENC_PIN1, PAL_MODE_INPUT_PULLUP);
palSetPadMode(HW_HALL_ENC_GPIO2, HW_HALL_ENC_PIN2, PAL_MODE_INPUT_PULLUP);
index_found = false;
mode = ENCODER_MODE_NONE;
last_enc_angle = 0.0;
}
/**
* @brief Disables EXTI IRQ sources.
*
* @notapi
*/
static void ext_lld_exti_irq_disable(void) {
#if KINETIS_EXT_PORTA_WIDTH > 0
nvicDisableVector(PINA_IRQn);
#endif
#if KINETIS_EXT_PORTB_WIDTH > 0
nvicDisableVector(PINB_IRQn);
#endif
#if KINETIS_EXT_PORTC_WIDTH > 0
nvicDisableVector(PINC_IRQn);
#endif
#if KINETIS_EXT_PORTD_WIDTH > 0
nvicDisableVector(PIND_IRQn);
#endif
#if KINETIS_EXT_PORTE_WIDTH > 0
nvicDisableVector(PINE_IRQn);
#endif
}
/** Disable USART RX DMA.
* \param s The USART DMA state structure.
*/
void usart_rx_dma_disable(usart_rx_dma_state* s)
{
/* Disable DMA stream interrupts with the NVIC. */
if (s->dma == DMA1)
nvicDisableVector(dma_irq_lookup[0][s->stream]);
else if (s->dma == DMA2)
nvicDisableVector(dma_irq_lookup[1][s->stream]);
/* Disable DMA stream. */
DMA_SCR(s->dma, s->stream) &= ~DMA_SxCR_EN;
while (DMA_SCR(s->dma, s->stream) & DMA_SxCR_EN) ;
/* Disable RX DMA on the USART. */
usart_disable_rx_dma(s->usart);
/* Clear the DMA transmit complete and half complete interrupt flags. */
dma_clear_interrupt_flags(s->dma, s->stream, DMA_HTIF | DMA_TCIF);
}
/**
* @brief Deactivates the SPI peripheral.
*
* @param[in] spip pointer to the @p SPIDriver object
*
* @notapi
*/
void spi_lld_stop(SPIDriver *spip) {
if (spip->state != SPI_STOP) {
spip->ssp->CR1 = 0;
spip->ssp->CR0 = 0;
spip->ssp->CPSR = 0;
#if LPC_SPI_USE_SSP0
if (&SPID1 == spip) {
LPC_CCU2->CLK_APB0_SSP0_CFG = 0;
nvicDisableVector(SSP0_IRQn);
}
#endif
#if LPC_SPI_USE_SSP1
if (&SPID2 == spip) {
LPC_CCU2->CLK_APB2_SSP1_CFG= 0;
nvicDisableVector(SSP1_IRQn);
}
#endif
}
}
/**
* @brief Deactivates the GPT peripheral.
*
* @param[in] gptp pointer to the @p GPTDriver object
*
* @notapi
*/
void gpt_lld_stop(GPTDriver *gptp) {
if (gptp->state == GPT_READY) {
gptp->tim->TASKS_SHUTDOWN = 1;
#if NRF5_GPT_USE_TIMER0
if (&GPTD1 == gptp)
nvicDisableVector(TIMER0_IRQn);
#endif
#if NRF5_GPT_USE_TIMER1
if (&GPTD2 == gptp)
nvicDisableVector(TIMER1_IRQn);
#endif
#if NRF5_GPT_USE_TIMER2
if (&GPTD3 == gptp)
nvicDisableVector(TIMER2_IRQn);
#endif
gptp->tim->INTENCLR = TIMER_INTENSET_COMPARE0_Msk << gptp->cc_int;
}
}
static void shutdown() {
// TODO: Is this complete?
nvicDisableVector(DMA_IRQn);
m0apptxevent_interrupt_disable();
chSysDisable();
systick_stop();
}
/**
* @brief Deactivates the PWM peripheral.
*
* @param[in] pwmp pointer to a @p PWMDriver object
*
* @notapi
*/
void pwm_lld_stop(PWMDriver *pwmp) {
pwmp->timer->TASKS_SHUTDOWN = 1;
#if NRF5_PWM_USE_TIMER0
if (&PWMD1 == pwmp) {
nvicDisableVector(TIMER0_IRQn);
}
#endif
#if NRF5_PWM_USE_TIMER1
if (&PWMD2 == pwmp) {
nvicDisableVector(TIMER1_IRQn);
}
#endif
#if NRF5_PWM_USE_TIMER2
if (&PWMD3 == pwmp) {
nvicDisableVector(TIMER2_IRQn);
}
#endif
}
/**
* @brief Low level serial driver stop.
* @details De-initializes the USART, stops the associated clock, resets the
* interrupt vector.
*
* @param[in] sdp pointer to a @p SerialDriver object
*
* @notapi
*/
void sd_lld_stop(SerialDriver *sdp) {
if (sdp->state == SD_READY) {
#if NRF51_SERIAL_USE_UART0 == TRUE
if (&SD1 == sdp) {
nvicDisableVector(UART0_IRQn);
NRF_UART0->ENABLE = UART_ENABLE_ENABLE_Disabled;
}
#endif
}
}
/**
* @brief Deactivates the I2C peripheral.
*
* @param[in] i2cp pointer to the @p I2CDriver object
*
* @notapi
*/
void i2c_lld_stop(I2CDriver *i2cp) {
/* If not in stopped state then disables the I2C clock.*/
if (i2cp->state != I2C_STOP) {
/* I2C disable.*/
i2c_lld_abort_operation(i2cp);
dmaStreamRelease(i2cp->dmatx);
dmaStreamRelease(i2cp->dmarx);
#if STM32_I2C_USE_I2C1
if (&I2CD1 == i2cp) {
nvicDisableVector(I2C1_EV_IRQn);
nvicDisableVector(I2C1_ER_IRQn);
rccDisableI2C1(FALSE);
}
#endif
#if STM32_I2C_USE_I2C2
if (&I2CD2 == i2cp) {
nvicDisableVector(I2C2_EV_IRQn);
nvicDisableVector(I2C2_ER_IRQn);
rccDisableI2C2(FALSE);
}
#endif
#if STM32_I2C_USE_I2C3
if (&I2CD3 == i2cp) {
nvicDisableVector(I2C3_EV_IRQn);
nvicDisableVector(I2C3_ER_IRQn);
rccDisableI2C3(FALSE);
}
#endif
}
}
/**
* @brief Low level serial driver stop.
* @details De-initializes the UART, stops the associated clock, resets the
* interrupt vector.
*
* @param[in] sdp pointer to a @p SerialDriver object
*
* @notapi
*/
void sd_lld_stop(SerialDriver *sdp) {
if (sdp->state == SD_READY) {
uart_deinit(sdp->uart);
#if LPC122x_SERIAL_USE_UART0
if (&SD1 == sdp) {
LPC_SYSCON->UART0CLKDIV = 0;
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 12);
nvicDisableVector(UART0_IRQn);
return;
}
#endif
#if LPC122x_SERIAL_USE_UART1
if (&SD2 == sdp) {
LPC_SYSCON->UART1CLKDIV = 0;
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 13);
nvicDisableVector(UART1_IRQn);
return;
}
#endif
}
}
/**
* @brief Deactivates the I2C peripheral.
*
* @param[in] i2cp pointer to the @p I2CDriver object
*
* @notapi
*/
void i2c_lld_stop(I2CDriver *i2cp) {
if (i2cp->state != I2C_STOP) {
i2cp->i2c->C1 &= ~(I2Cx_C1_IICEN | I2Cx_C1_IICIE);
#if KINETIS_I2C_USE_I2C0
if (&I2CD1 == i2cp) {
SIM->SCGC4 &= ~SIM_SCGC4_I2C0;
nvicDisableVector(I2C0_IRQn);
}
#endif
#if KINETIS_I2C_USE_I2C1
if (&I2CD2 == i2cp) {
SIM->SCGC4 &= ~SIM_SCGC4_I2C1;
nvicDisableVector(I2C1_IRQn);
}
#endif
}
}
