static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt)
{
/* Select ACPI logical device, enable it and CIR Wake */
nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
/* Enable CIR Wake via PSOUT# (Pin60) */
nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
/* enable cir interrupt of mouse/keyboard IRQ event */
nvt_set_reg_bit(nvt, CIR_INTR_MOUSE_IRQ_BIT, CR_ACPI_IRQ_EVENTS);
/* enable pme interrupt of cir wakeup event */
nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
/* Select CIR Wake logical device and enable */
nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
nvt_cr_write(nvt, nvt->cir_wake_addr >> 8, CR_CIR_BASE_ADDR_HI);
nvt_cr_write(nvt, nvt->cir_wake_addr & 0xff, CR_CIR_BASE_ADDR_LO);
nvt_cr_write(nvt, nvt->cir_wake_irq, CR_CIR_IRQ_RSRC);
nvt_dbg("CIR Wake initialized, base io port address: 0x%lx, irq: %d",
nvt->cir_wake_addr, nvt->cir_wake_irq);
}
static void nvt_cir_ldev_init(struct nvt_dev *nvt)
{
u8 val, psreg, psmask, psval;
if (is_w83667hg(nvt)) {
psreg = CR_MULTIFUNC_PIN_SEL;
psmask = MULTIFUNC_PIN_SEL_MASK;
psval = MULTIFUNC_ENABLE_CIR | MULTIFUNC_ENABLE_CIRWB;
} else {
psreg = CR_OUTPUT_PIN_SEL;
psmask = OUTPUT_PIN_SEL_MASK;
psval = OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB;
}
/* output pin selection: enable CIR, with WB sensor enabled */
val = nvt_cr_read(nvt, psreg);
val &= psmask;
val |= psval;
nvt_cr_write(nvt, val, psreg);
/* Select CIR logical device and enable */
nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
nvt_cr_write(nvt, nvt->cir_addr >> 8, CR_CIR_BASE_ADDR_HI);
nvt_cr_write(nvt, nvt->cir_addr & 0xff, CR_CIR_BASE_ADDR_LO);
nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
nvt->cir_addr, nvt->cir_irq);
}
/* detect hardware features */
static int nvt_hw_detect(struct nvt_dev *nvt)
{
unsigned long flags;
u8 chip_major, chip_minor;
int ret = 0;
nvt_efm_enable(nvt);
/* Check if we're wired for the alternate EFER setup */
chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
if (chip_major == 0xff) {
nvt->cr_efir = CR_EFIR2;
nvt->cr_efdr = CR_EFDR2;
nvt_efm_enable(nvt);
chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
}
chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
nvt_dbg("%s: chip id: 0x%02x 0x%02x", chip_id, chip_major, chip_minor);
if (chip_major != CHIP_ID_HIGH &&
(chip_minor != CHIP_ID_LOW || chip_minor != CHIP_ID_LOW2))
ret = -ENODEV;
nvt_efm_disable(nvt);
spin_lock_irqsave(&nvt->nvt_lock, flags);
nvt->chip_major = chip_major;
nvt->chip_minor = chip_minor;
spin_unlock_irqrestore(&nvt->nvt_lock, flags);
return ret;
}
static void nvt_cir_ldev_init(struct nvt_dev *nvt)
{
u8 val;
/* output pin selection (Pin95=CIRRX, Pin96=CIRTX1, WB enabled */
val = nvt_cr_read(nvt, CR_OUTPUT_PIN_SEL);
val &= OUTPUT_PIN_SEL_MASK;
val |= (OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB);
nvt_cr_write(nvt, val, CR_OUTPUT_PIN_SEL);
/* Select CIR logical device and enable */
nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
nvt_cr_write(nvt, nvt->cir_addr >> 8, CR_CIR_BASE_ADDR_HI);
nvt_cr_write(nvt, nvt->cir_addr & 0xff, CR_CIR_BASE_ADDR_LO);
nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
nvt->cir_addr, nvt->cir_irq);
}
/* detect hardware features */
static int nvt_hw_detect(struct nvt_dev *nvt)
{
unsigned long flags;
u8 chip_major, chip_minor;
int ret = 0;
char chip_id[12];
bool chip_unknown = false;
nvt_efm_enable(nvt);
/* Check if we're wired for the alternate EFER setup */
chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
if (chip_major == 0xff) {
nvt->cr_efir = CR_EFIR2;
nvt->cr_efdr = CR_EFDR2;
nvt_efm_enable(nvt);
chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
}
chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
/* these are the known working chip revisions... */
switch (chip_major) {
case CHIP_ID_HIGH_667:
strcpy(chip_id, "w83667hg\0");
if (chip_minor != CHIP_ID_LOW_667)
chip_unknown = true;
break;
case CHIP_ID_HIGH_677B:
strcpy(chip_id, "w83677hg\0");
if (chip_minor != CHIP_ID_LOW_677B2 &&
chip_minor != CHIP_ID_LOW_677B3)
chip_unknown = true;
break;
case CHIP_ID_HIGH_677C:
strcpy(chip_id, "w83677hg-c\0");
if (chip_minor != CHIP_ID_LOW_677C)
chip_unknown = true;
break;
default:
strcpy(chip_id, "w836x7hg\0");
chip_unknown = true;
break;
}
/* warn, but still let the driver load, if we don't know this chip */
if (chip_unknown)
nvt_pr(KERN_WARNING, "%s: unknown chip, id: 0x%02x 0x%02x, "
"it may not work...", chip_id, chip_major, chip_minor);
else
nvt_dbg("%s: chip id: 0x%02x 0x%02x",
chip_id, chip_major, chip_minor);
nvt_efm_disable(nvt);
spin_lock_irqsave(&nvt->nvt_lock, flags);
nvt->chip_major = chip_major;
nvt->chip_minor = chip_minor;
spin_unlock_irqrestore(&nvt->nvt_lock, flags);
return ret;
}
