static void __init yucca_set_emacdata(void)
{
struct ocp_def *def;
struct ocp_func_emac_data *emacdata;
/* Set phy_map, phy_mode, and mac_addr for the EMAC */
def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
emacdata = def->additions;
emacdata->phy_map = 0x00000001; /* Skip 0x00 */
emacdata->phy_mode = PHY_MODE_GMII;
memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
}
static void __init ocotea_set_emacdata(void)
{
struct ocp_def *def;
struct ocp_func_emac_data *emacdata;
int i;
/*
* Note: Current rev. board only operates in Group 4a
* mode, so we always set EMAC0-1 for SMII and EMAC2-3
* for RGMII (though these could run in RTBI just the same).
*
* The FPGA reg 3 information isn't even suitable for
* determining the phy_mode, so if the board becomes
* usable in !4a, it will be necessary to parse an environment
* variable from the firmware or similar to properly configure
* the phy_map/phy_mode.
*/
/* Set phy_map, phy_mode, and mac_addr for each EMAC */
for (i=0; i<4; i++) {
def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i);
emacdata = def->additions;
if (i < 2) {
emacdata->phy_map = 0x00000001; /* Skip 0x00 */
emacdata->phy_mode = PHY_MODE_SMII;
}
else {
emacdata->phy_map = 0x0000ffff; /* Skip 0x00-0x0f */
emacdata->phy_mode = PHY_MODE_RGMII;
}
if (i == 0)
memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
else if (i == 1)
memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
else if (i == 2)
memcpy(emacdata->mac_addr, __res.bi_enet2addr, 6);
else if (i == 3)
memcpy(emacdata->mac_addr, __res.bi_enet3addr, 6);
}
}
static void __init bamboo_set_emacdata(void)
{
u8 * base_addr;
struct ocp_def *def;
struct ocp_func_emac_data *emacdata;
u8 val;
int mode;
u32 excluded = 0;
base_addr = ioremap64(BAMBOO_FPGA_SELECTION1_REG_ADDR, 16);
val = readb(base_addr);
iounmap((void *) base_addr);
if (BAMBOO_SEL_MII(val))
mode = PHY_MODE_MII;
else if (BAMBOO_SEL_RMII(val))
mode = PHY_MODE_RMII;
else
mode = PHY_MODE_SMII;
/*
* SW2 on the Bamboo is used for ethernet configuration and is accessed
* via the CONFIG2 register in the FPGA. If the ANEG pin is set,
* overwrite the supported features with the settings in SW2.
*
* This is used as a workaround for the improperly biased RJ-45 sockets
* on the Rev. 0 Bamboo. By default only 10baseT is functional.
* Removing inductors L17 and L18 from the board allows 100baseT, but
* disables 10baseT. The Rev. 1 has no such limitations.
*/
base_addr = ioremap64(BAMBOO_FPGA_CONFIG2_REG_ADDR, 8);
val = readb(base_addr);
iounmap((void *) base_addr);
if (!BAMBOO_AUTONEGOTIATE(val)) {
excluded |= SUPPORTED_Autoneg;
if (BAMBOO_FORCE_100Mbps(val)) {
excluded |= SUPPORTED_10baseT_Full;
excluded |= SUPPORTED_10baseT_Half;
if (BAMBOO_FULL_DUPLEX_EN(val))
excluded |= SUPPORTED_100baseT_Half;
else
excluded |= SUPPORTED_100baseT_Full;
} else {
excluded |= SUPPORTED_100baseT_Full;
excluded |= SUPPORTED_100baseT_Half;
if (BAMBOO_FULL_DUPLEX_EN(val))
excluded |= SUPPORTED_10baseT_Half;
else
excluded |= SUPPORTED_10baseT_Full;
}
}
/* Set mac_addr, phy mode and unsupported phy features for each EMAC */
def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
emacdata = def->additions;
memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
emacdata->phy_mode = mode;
emacdata->phy_feat_exc = excluded;
def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
emacdata = def->additions;
memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
emacdata->phy_mode = mode;
emacdata->phy_feat_exc = excluded;
}
/* ************************************************************************
*
* Setup the architecture
*
*/
static void __init
mpc8540ads_setup_arch(void)
{
struct ocp_def *def;
struct ocp_gfar_data *einfo;
bd_t *binfo = (bd_t *) __res;
unsigned int freq;
/* get the core frequency */
freq = binfo->bi_intfreq;
if (ppc_md.progress)
ppc_md.progress("mpc8540ads_setup_arch()", 0);
/* Set loops_per_jiffy to a half-way reasonable value,
for use until calibrate_delay gets called. */
loops_per_jiffy = freq / HZ;
#ifdef CONFIG_PCI
/* setup PCI host bridges */
mpc85xx_setup_hose();
#endif
#ifdef CONFIG_SERIAL_8250
mpc85xx_early_serial_map();
#endif
#ifdef CONFIG_SERIAL_TEXT_DEBUG
/* Invalidate the entry we stole earlier the serial ports
* should be properly mapped */
invalidate_tlbcam_entry(NUM_TLBCAMS - 1);
#endif
def = ocp_get_one_device(OCP_VENDOR_FREESCALE, OCP_FUNC_GFAR, 0);
if (def) {
einfo = (struct ocp_gfar_data *) def->additions;
memcpy(einfo->mac_addr, binfo->bi_enetaddr, 6);
}
def = ocp_get_one_device(OCP_VENDOR_FREESCALE, OCP_FUNC_GFAR, 1);
if (def) {
einfo = (struct ocp_gfar_data *) def->additions;
memcpy(einfo->mac_addr, binfo->bi_enet1addr, 6);
}
def = ocp_get_one_device(OCP_VENDOR_FREESCALE, OCP_FUNC_GFAR, 2);
if (def) {
einfo = (struct ocp_gfar_data *) def->additions;
memcpy(einfo->mac_addr, binfo->bi_enet2addr, 6);
}
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_HDA1;
#endif
ocp_for_each_device(mpc85xx_update_paddr_ocp, &(binfo->bi_immr_base));
}
