/* Abort all chained DMA transfers. After all transfers have been
* aborted and the DMA controller is idle, the completion routines for
* any aborted transfers will be called in sequence. The DMA
* controller may not be idle after this routine completes, because
* the completion routines might start new transfers.
*/
static void omap24xxcam_dmahw_abort_ch(void __iomem *base, int dmach)
{
/* mask all interrupts from this channel */
omap24xxcam_reg_out(base, CAMDMA_CICR(dmach), 0);
/* unlink this channel */
omap24xxcam_reg_merge(base, CAMDMA_CLNK_CTRL(dmach), 0,
CAMDMA_CLNK_CTRL_ENABLE_LNK);
/* disable this channel */
omap24xxcam_reg_merge(base, CAMDMA_CCR(dmach), 0, CAMDMA_CCR_ENABLE);
}
static void omap24xxcam_dmahw_abort_ch(unsigned long base, int dmach)
{
omap24xxcam_reg_out(base, CAMDMA_CICR(dmach), 0);
omap24xxcam_reg_merge(base, CAMDMA_CLNK_CTRL(dmach), 0,
CAMDMA_CLNK_CTRL_ENABLE_LNK);
omap24xxcam_reg_merge(base, CAMDMA_CCR(dmach), 0, CAMDMA_CCR_ENABLE);
}
static void omap24xxcam_dmahw_init(void __iomem *base)
{
omap24xxcam_reg_out(base, CAMDMA_OCP_SYSCONFIG,
CAMDMA_OCP_SYSCONFIG_MIDLEMODE_FSTANDBY
| CAMDMA_OCP_SYSCONFIG_SIDLEMODE_FIDLE
| CAMDMA_OCP_SYSCONFIG_AUTOIDLE);
omap24xxcam_reg_merge(base, CAMDMA_GCR, 0x10,
CAMDMA_GCR_MAX_CHANNEL_FIFO_DEPTH);
omap24xxcam_reg_out(base, CAMDMA_IRQENABLE_L0, 0xf);
}
