int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
{
if (!clk->clksel)
return -EINVAL;
if (clk->parent == new_parent)
return 0;
return omap2_clksel_set_parent(clk, new_parent);
}
/* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
* physically present, in such a case HWMOD enabling of
* clock would be failure with default parent. And timer
* probe thinks clock is already enabled, this leads to
* crash upon accessing timer 3 & 6 registers in probe.
* Fix by setting parent of both these timers to master
* oscillator clock.
*/
static inline void am33xx_init_timer_parent(struct clk *clk)
{
omap2_clksel_set_parent(clk, clk->parent);
}
static int clkout_clksel_set_parent(struct clk_hw *hw, u8 field_val)
{
return omap2_clksel_set_parent(hw, field_val);
}
