void __init omap_init_irq(void)
{
unsigned long nr_of_irqs = 0;
unsigned int nr_banks = 0;
int i;
for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
struct omap_irq_bank *bank = irq_banks + i;
if (cpu_is_omapw3g())
bank->base_reg = OMAP2_IO_ADDRESS(OMAPW3G_IC_BASE);
else if (cpu_is_omap24xx())
bank->base_reg = OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE);
else if (cpu_is_omap34xx())
bank->base_reg = OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE);
omap_irq_bank_init_one(bank);
nr_of_irqs += bank->nr_irqs;
nr_banks++;
}
printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
for (i = 0; i < nr_of_irqs; i++) {
/* Regardless of reserved IRQ, the interrupt must be handled using kernel's main irq handler */
omap_irq_set_cfg(i, 0, irq_priority[i]);
set_irq_chip(i, &omap_irq_chip);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
}
void __init omap_init_irq(void)
{
int i, j;
#ifdef CONFIG_ARCH_OMAP730
if (cpu_is_omap730()) {
irq_banks = omap730_irq_banks;
irq_bank_count = ARRAY_SIZE(omap730_irq_banks);
}
#endif
#ifdef CONFIG_ARCH_OMAP15XX
if (cpu_is_omap1510()) {
irq_banks = omap1510_irq_banks;
irq_bank_count = ARRAY_SIZE(omap1510_irq_banks);
}
if (cpu_is_omap310()) {
irq_banks = omap310_irq_banks;
irq_bank_count = ARRAY_SIZE(omap310_irq_banks);
}
#endif
#if defined(CONFIG_ARCH_OMAP16XX)
if (cpu_is_omap16xx()) {
irq_banks = omap1610_irq_banks;
irq_bank_count = ARRAY_SIZE(omap1610_irq_banks);
}
#endif
printk("Total of %i interrupts in %i interrupt banks\n",
irq_bank_count * 32, irq_bank_count);
/* Mask and clear all interrupts */
for (i = 0; i < irq_bank_count; i++) {
irq_bank_writel(~0x0, i, IRQ_MIR_REG_OFFSET);
irq_bank_writel(0x0, i, IRQ_ITR_REG_OFFSET);
}
/* Clear any pending interrupts */
irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET);
irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET);
/* Enable interrupts in global mask */
if (cpu_is_omap730()) {
irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET);
}
/* Install the interrupt handlers for each bank */
for (i = 0; i < irq_bank_count; i++) {
for (j = i * 32; j < (i + 1) * 32; j++) {
int irq_trigger;
irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j);
omap_irq_set_cfg(j, 0, 0, irq_trigger);
set_irq_chip(j, &omap_irq_chip);
set_irq_handler(j, handle_level_irq);
set_irq_flags(j, IRQF_VALID);
}
}
/* Unmask level 2 handler */
if (cpu_is_omap730())
omap_unmask_irq(INT_730_IH2_IRQ);
else if (cpu_is_omap15xx())
omap_unmask_irq(INT_1510_IH2_IRQ);
else if (cpu_is_omap16xx())
omap_unmask_irq(INT_1610_IH2_IRQ);
}