/*
* Function called when the module is initialized
*/
static int __init dma_module_init(void) {
int error;
int i = 0;
/* Request a chain */
chain.chain_type = OMAP_DMA_DYNAMIC_CHAIN;
chain.device_id = OMAP_DMA_NO_DEVICE;
chain.data_type = OMAP_DMA_DATA_TYPE_S8;
chain.addressing_mode = OMAP_DMA_AMODE_POST_INC;
chain.sync_mode = OMAP_DMA_SYNC_ELEMENT;
chain.data_burst = OMAP_DMA_DATA_BURST_DIS;
chain.channel_count = TRANSFER_COUNT;
error = request_dma_chain(&chain);
omap_set_dma_callback(chain.chain_id, dma_callback_chain, &transfers);
if(error){
set_test_passed_chain(0);
return 1;
}
for(i = 0; i < 1/*chain.channel_count*/; i++){
/* Create the buffers for each transfer */
transfers[i].buffers.buf_size = (1024 * 1);
error = create_transfer_buffers_chain(&(transfers[i].buffers));
if( error ){
set_test_passed_chain(0);
return 1;
}
fill_source_buffer_chain(&(transfers[i].buffers));
/* Chain the first transfer to the chain */
error = chain_transfer(&chain, &transfers[i]);
if( error ){
set_test_passed_chain(0);
return 1;
}
}
/* The first chained transfer has index 0, 1 points to the next one */
current_transfer = 1;
/* Setup the global dma parameters */
setup_dma_chain(&chain);
/* Start the chain */
start_dma_chain(&chain);
/* Poll if the all the transfers have finished */
for(i = 0; i < TRANSFER_POLL_COUNT; i++){
if(get_transfers_finished()){
mdelay(TRANSFER_POLL_TIME);
check_test_passed();
break;
}else{
mdelay(TRANSFER_POLL_TIME);
}
}
/* This will happen if the poll retries have been reached*/
if(i == TRANSFER_POLL_COUNT){
set_test_passed_chain(0);
return 1;
}
return 0;
}
static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
u8 rndis_mode, dma_addr_t dma_addr, u32 len)
{
struct tusb_omap_dma_ch *chdat = to_chdat(channel);
struct tusb_omap_dma *tusb_dma = chdat->tusb_dma;
struct musb *musb = chdat->musb;
struct device *dev = musb->controller;
struct musb_hw_ep *hw_ep = chdat->hw_ep;
void __iomem *mbase = musb->mregs;
void __iomem *ep_conf = hw_ep->conf;
dma_addr_t fifo = hw_ep->fifo_sync;
struct omap_dma_channel_params dma_params;
u32 dma_remaining;
int src_burst, dst_burst;
u16 csr;
int ch;
s8 dmareq;
s8 sync_dev;
if (unlikely(dma_addr & 0x1) || (len < 32) || (len > packet_sz))
return false;
/*
* HW issue #10: Async dma will eventually corrupt the XFR_SIZE
* register which will cause missed DMA interrupt. We could try to
* use a timer for the callback, but it is unsafe as the XFR_SIZE
* register is corrupt, and we won't know if the DMA worked.
*/
if (dma_addr & 0x2)
return false;
/*
* Because of HW issue #10, it seems like mixing sync DMA and async
* PIO access can confuse the DMA. Make sure XFR_SIZE is reset before
* using the channel for DMA.
*/
if (chdat->tx)
dma_remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET);
else
dma_remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET);
dma_remaining = TUSB_EP_CONFIG_XFR_SIZE(dma_remaining);
if (dma_remaining) {
dev_dbg(musb->controller, "Busy %s dma ch%i, not using: %08x\n",
chdat->tx ? "tx" : "rx", chdat->ch,
dma_remaining);
return false;
}
chdat->transfer_len = len & ~0x1f;
if (len < packet_sz)
chdat->transfer_packet_sz = chdat->transfer_len;
else
chdat->transfer_packet_sz = packet_sz;
if (tusb_dma->multichannel) {
ch = chdat->ch;
dmareq = chdat->dmareq;
sync_dev = chdat->sync_dev;
} else {
if (tusb_omap_use_shared_dmareq(chdat) != 0) {
dev_dbg(musb->controller, "could not get dma for ep%i\n", chdat->epnum);
return false;
}
if (tusb_dma->ch < 0) {
/* REVISIT: This should get blocked earlier, happens
* with MSC ErrorRecoveryTest
*/
WARN_ON(1);
return false;
}
ch = tusb_dma->ch;
dmareq = tusb_dma->dmareq;
sync_dev = tusb_dma->sync_dev;
omap_set_dma_callback(ch, tusb_omap_dma_cb, channel);
}
chdat->packet_sz = packet_sz;
chdat->len = len;
channel->actual_len = 0;
chdat->dma_addr = dma_addr;
channel->status = MUSB_DMA_STATUS_BUSY;
/* Since we're recycling dma areas, we need to clean or invalidate */
if (chdat->tx)
dma_map_single(dev, phys_to_virt(dma_addr), len,
DMA_TO_DEVICE);
else
dma_map_single(dev, phys_to_virt(dma_addr), len,
DMA_FROM_DEVICE);
/* Use 16-bit transfer if dma_addr is not 32-bit aligned */
if ((dma_addr & 0x3) == 0) {
dma_params.data_type = OMAP_DMA_DATA_TYPE_S32;
dma_params.elem_count = 8; /* Elements in frame */
} else {
dma_params.data_type = OMAP_DMA_DATA_TYPE_S16;
dma_params.elem_count = 16; /* Elements in frame */
fifo = hw_ep->fifo_async;
}
dma_params.frame_count = chdat->transfer_len / 32; /* Burst sz frame */
dev_dbg(musb->controller, "ep%i %s dma ch%i dma: %08x len: %u(%u) packet_sz: %i(%i)\n",
chdat->epnum, chdat->tx ? "tx" : "rx",
ch, dma_addr, chdat->transfer_len, len,
chdat->transfer_packet_sz, packet_sz);
/*
* Prepare omap DMA for transfer
*/
if (chdat->tx) {
dma_params.src_amode = OMAP_DMA_AMODE_POST_INC;
dma_params.src_start = (unsigned long)dma_addr;
dma_params.src_ei = 0;
dma_params.src_fi = 0;
dma_params.dst_amode = OMAP_DMA_AMODE_DOUBLE_IDX;
dma_params.dst_start = (unsigned long)fifo;
dma_params.dst_ei = 1;
dma_params.dst_fi = -31; /* Loop 32 byte window */
dma_params.trigger = sync_dev;
dma_params.sync_mode = OMAP_DMA_SYNC_FRAME;
dma_params.src_or_dst_synch = 0; /* Dest sync */
src_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 read */
dst_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 write */
} else {
dma_params.src_amode = OMAP_DMA_AMODE_DOUBLE_IDX;
dma_params.src_start = (unsigned long)fifo;
dma_params.src_ei = 1;
dma_params.src_fi = -31; /* Loop 32 byte window */
dma_params.dst_amode = OMAP_DMA_AMODE_POST_INC;
dma_params.dst_start = (unsigned long)dma_addr;
dma_params.dst_ei = 0;
dma_params.dst_fi = 0;
dma_params.trigger = sync_dev;
dma_params.sync_mode = OMAP_DMA_SYNC_FRAME;
dma_params.src_or_dst_synch = 1; /* Source sync */
src_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 read */
dst_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 write */
}
dev_dbg(musb->controller, "ep%i %s using %i-bit %s dma from 0x%08lx to 0x%08lx\n",
chdat->epnum, chdat->tx ? "tx" : "rx",
(dma_params.data_type == OMAP_DMA_DATA_TYPE_S32) ? 32 : 16,
((dma_addr & 0x3) == 0) ? "sync" : "async",
dma_params.src_start, dma_params.dst_start);
omap_set_dma_params(ch, &dma_params);
omap_set_dma_src_burst_mode(ch, src_burst);
omap_set_dma_dest_burst_mode(ch, dst_burst);
omap_set_dma_write_mode(ch, OMAP_DMA_WRITE_LAST_NON_POSTED);
/*
* Prepare MUSB for DMA transfer
*/
if (chdat->tx) {
musb_ep_select(mbase, chdat->epnum);
csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
csr |= (MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB
| MUSB_TXCSR_DMAMODE | MUSB_TXCSR_MODE);
csr &= ~MUSB_TXCSR_P_UNDERRUN;
musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
} else {
musb_ep_select(mbase, chdat->epnum);
csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
csr |= MUSB_RXCSR_DMAENAB;
csr &= ~(MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAMODE);
musb_writew(hw_ep->regs, MUSB_RXCSR,
csr | MUSB_RXCSR_P_WZC_BITS);
}
/*
* Start DMA transfer
*/
omap_start_dma(ch);
if (chdat->tx) {
/* Send transfer_packet_sz packets at a time */
musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET,
chdat->transfer_packet_sz);
musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len));
} else {
/* Receive transfer_packet_sz packets at a time */
musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET,
chdat->transfer_packet_sz << 16);
musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len));
}
return true;
}
int dma_chain_thread_entry(void *info)
{
int error;
int i = 0;
struct chain_transfer *ct = (struct chain_transfer *)info;
/* Request a chain */
ct->chain.chain_type = OMAP_DMA_DYNAMIC_CHAIN;
ct->chain.device_id = OMAP_DMA_NO_DEVICE;
ct->chain.data_type = OMAP_DMA_DATA_TYPE_S8;
ct->chain.addressing_mode = OMAP_DMA_AMODE_POST_INC;
ct->chain.sync_mode = OMAP_DMA_SYNC_ELEMENT;
ct->chain.data_burst = OMAP_DMA_DATA_BURST_DIS;
ct->chain.channel_count = TRANSFER_COUNT;
error = request_dma_chain(&(ct->chain));
omap_set_dma_callback(ct->chain.chain_id, dma_callback_chain, ct);
if (error) {
set_test_passed_chain(0);
return 1;
}
for (i = 0; i < 1/*chain.channel_count*/; i++) {
/* Create the buffers for each transfer */
ct->transfers[i].buffers.buf_size = (1024 * 1);
error = create_transfer_buffers_chain(
&(ct->transfers[i].buffers));
if (error) {
set_test_passed_chain(0);
return 1;
}
fill_source_buffer_chain(&(ct->transfers[i].buffers));
/* Chain the first transfer to the chain */
error = chain_transfer(&(ct->chain), &(ct->transfers[i]));
if (error) {
set_test_passed_chain(0);
return 1;
}
}
ct->current_transfer = 0;
/* Setup the global dma parameters */
setup_dma_chain(&(ct->chain));
/* Start the chain */
start_dma_chain(&(ct->chain));
/* Poll if the all the transfers have finished */
for (i = 0; i < TRANSFER_POLL_COUNT; i++) {
if (ct->transfer_end) {
mdelay(TRANSFER_POLL_TIME);
printk("Thread %d :", thread_count);
check_test_passed(ct->transfers);
break;
} else {
mdelay(TRANSFER_POLL_TIME);
}
}
/* This will happen if the poll retries have been reached*/
if (i == TRANSFER_POLL_COUNT) {
set_test_passed_chain(0);
return 1;
}
count += 1;
thread_count += 1;
return 0;
}