/*
* Identify device ID and rev from PCIe configuration header space '0'.
*/
static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
{
orion5x_pcie_id(dev, rev);
if (*dev == MV88F5281_DEV_ID) {
if (*rev == MV88F5281_REV_D2) {
*dev_name = "MV88F5281-D2";
} else if (*rev == MV88F5281_REV_D1) {
*dev_name = "MV88F5281-D1";
} else {
*dev_name = "MV88F5281-Rev-Unsupported";
}
} else if (*dev == MV88F5182_DEV_ID) {
if (*rev == MV88F5182_REV_A2) {
*dev_name = "MV88F5182-A2";
} else {
*dev_name = "MV88F5182-Rev-Unsupported";
}
} else if (*dev == MV88F5181_DEV_ID) {
if (*rev == MV88F5181_REV_B1) {
*dev_name = "MV88F5181-Rev-B1";
} else {
*dev_name = "MV88F5181-Rev-Unsupported";
}
} else {
*dev_name = "Device-Unknown";
}
}
static int __init orion5x_find_tclk(void)
{
u32 dev, rev;
orion5x_pcie_id(&dev, &rev);
if (dev == MV88F6183_DEV_ID &&
(readl(MPP_RESET_SAMPLE) & 0x00000200) == 0)
return 133333333;
return 166666667;
}
static int __init orion5x_cpu_win_can_remap(int win)
{
u32 dev, rev;
orion5x_pcie_id(&dev, &rev);
if ((dev == MV88F5281_DEV_ID && win < 4)
|| (dev == MV88F5182_DEV_ID && win < 2)
|| (dev == MV88F5181_DEV_ID && win < 2))
return 1;
return 0;
}
static int __init cpu_win_can_remap(const struct orion_addr_map_cfg *cfg,
const int win)
{
u32 dev, rev;
orion5x_pcie_id(&dev, &rev);
if ((dev == MV88F5281_DEV_ID && win < 4)
|| (dev == MV88F5182_DEV_ID && win < 2)
|| (dev == MV88F5181_DEV_ID && win < 2)
|| (dev == MV88F6183_DEV_ID && win < 4))
return 1;
return 0;
}
static unsigned int __init orion5x_variant(void)
{
u32 dev;
u32 rev;
orion5x_pcie_id(&dev, &rev);
if (dev == MV88F5181_DEV_ID)
return MPP_F5181_MASK;
if (dev == MV88F5182_DEV_ID)
return MPP_F5182_MASK;
if (dev == MV88F5281_DEV_ID)
return MPP_F5281_MASK;
printk(KERN_ERR "MPP setup: unknown orion5x variant "
"(dev %#x rev %#x)\n", dev, rev);
return 0;
}
/*****************************************************************************
* Time handling
****************************************************************************/
void __init orion5x_init_early(void)
{
u32 rev, dev;
const char *mbus_soc_name;
orion_time_set_base(TIMER_VIRT_BASE);
/* Initialize the MBUS driver */
orion5x_pcie_id(&dev, &rev);
if (dev == MV88F5281_DEV_ID)
mbus_soc_name = "marvell,orion5x-88f5281-mbus";
else if (dev == MV88F5182_DEV_ID)
mbus_soc_name = "marvell,orion5x-88f5182-mbus";
else if (dev == MV88F5181_DEV_ID)
mbus_soc_name = "marvell,orion5x-88f5181-mbus";
else if (dev == MV88F6183_DEV_ID)
mbus_soc_name = "marvell,orion5x-88f6183-mbus";
else
mbus_soc_name = NULL;
mvebu_mbus_init(mbus_soc_name, ORION5X_BRIDGE_WINS_BASE,
ORION5X_BRIDGE_WINS_SZ,
ORION5X_DDR_WINS_BASE, ORION5X_DDR_WINS_SZ);
}
static int __init dns323_identify_rev(void)
{
u32 dev, rev, i, reg;
pr_debug("DNS-323: Identifying board ... \n");
/* Rev A1 has a 5181 */
orion5x_pcie_id(&dev, &rev);
if (dev == MV88F5181_DEV_ID) {
pr_debug("DNS-323: 5181 found, board is A1\n");
return DNS323_REV_A1;
}
pr_debug("DNS-323: 5182 found, board is B1 or C1, checking PHY...\n");
/* Rev B1 and C1 both have 5182, let's poke at the eth PHY. This is
* a bit gross but we want to do that without links into the eth
* driver so let's poke at it directly. We default to rev B1 in
* case the accesses fail
*/
#define ETH_SMI_REG (ORION5X_ETH_VIRT_BASE + 0x2000 + 0x004)
#define SMI_BUSY 0x10000000
#define SMI_READ_VALID 0x08000000
#define SMI_OPCODE_READ 0x04000000
#define SMI_OPCODE_WRITE 0x00000000
for (i = 0; i < 1000; i++) {
reg = readl(ETH_SMI_REG);
if (!(reg & SMI_BUSY))
break;
}
if (i >= 1000) {
pr_warning("DNS-323: Timeout accessing PHY, assuming rev B1\n");
return DNS323_REV_B1;
}
writel((3 << 21) /* phy ID reg */ |
(8 << 16) /* phy addr */ |
SMI_OPCODE_READ, ETH_SMI_REG);
for (i = 0; i < 1000; i++) {
reg = readl(ETH_SMI_REG);
if (reg & SMI_READ_VALID)
break;
}
if (i >= 1000) {
pr_warning("DNS-323: Timeout reading PHY, assuming rev B1\n");
return DNS323_REV_B1;
}
pr_debug("DNS-323: Ethernet PHY ID 0x%x\n", reg & 0xffff);
/* Note: the Marvell tools mask the ID with 0x3f0 before comparison
* but I don't see that making a difference here, at least with
* any known Marvell PHY ID
*/
switch(reg & 0xfff0) {
case 0x0cc0: /* MV88E1111 */
return DNS323_REV_B1;
case 0x0e10: /* MV88E1118 */
return DNS323_REV_C1;
default:
pr_warning("DNS-323: Unknown PHY ID 0x%04x, assuming rev B1\n",
reg & 0xffff);
}
return DNS323_REV_B1;
}
