/*
* Collect the submitted frames and inform the application about them
* It is also preparing the TDs for new frames. If the Tx interrupts
* are disabled, the application should call that routine to get
* confirmation about the submitted frames. Otherwise, the routine is
* called frome the interrupt service routine during the Tx interrupt.
* In that case the application is informed by calling the application
* specific 'fhci_transaction_confirm' routine
*/
static void fhci_td_transaction_confirm(struct fhci_usb *usb)
{
struct endpoint *ep = usb->ep0;
struct packet *pkt;
struct usb_td __iomem *td;
u16 extra_data;
u16 td_status;
u16 td_length;
u32 buf;
/*
* collect transmitted BDs from the chip. The routine clears all BDs
* with R bit = 0 and the pointer to data buffer is not NULL, that is
* BDs which point to the transmitted data buffer
*/
while (1) {
td = ep->conf_td;
td_status = in_be16(&td->status);
td_length = in_be16(&td->length);
buf = in_be32(&td->buf_ptr);
extra_data = in_be16(&td->extra);
/* check if the TD is empty */
if (!(!(td_status & TD_R) && ((td_status & ~TD_W) || buf)))
break;
/* check if it is a dummy buffer */
else if ((buf == DUMMY_BD_BUFFER) && !(td_status & ~TD_W))
break;
/* mark TD as empty */
clrbits16(&td->status, ~TD_W);
out_be16(&td->length, 0);
out_be32(&td->buf_ptr, 0);
out_be16(&td->extra, 0);
/* advance the TD pointer */
ep->conf_td = next_bd(ep->td_base, ep->conf_td, td_status);
/* check if it is a dummy buffer(type2) */
if ((buf == DUMMY2_BD_BUFFER) && !(td_status & ~TD_W))
continue;
pkt = cq_get(&ep->conf_frame_Q);
if (!pkt)
fhci_err(usb->fhci, "no frame to confirm\n");
if (td_status & TD_ERRORS) {
if (td_status & TD_RXER) {
if (td_status & TD_CR)
pkt->status = USB_TD_RX_ER_CRC;
else if (td_status & TD_AB)
pkt->status = USB_TD_RX_ER_BITSTUFF;
else if (td_status & TD_OV)
pkt->status = USB_TD_RX_ER_OVERUN;
else if (td_status & TD_BOV)
pkt->status = USB_TD_RX_DATA_OVERUN;
else if (td_status & TD_NO)
pkt->status = USB_TD_RX_ER_NONOCT;
else
fhci_err(usb->fhci, "illegal error "
"occured\n");
} else if (td_status & TD_NAK)
pkt->status = USB_TD_TX_ER_NAK;
else if (td_status & TD_TO)
pkt->status = USB_TD_TX_ER_TIMEOUT;
else if (td_status & TD_UN)
pkt->status = USB_TD_TX_ER_UNDERUN;
else if (td_status & TD_STAL)
pkt->status = USB_TD_TX_ER_STALL;
else
fhci_err(usb->fhci, "illegal error occured\n");
} else if ((extra_data & TD_TOK_IN) &&
pkt->len > td_length - CRC_SIZE) {
pkt->status = USB_TD_RX_DATA_UNDERUN;
}
if (extra_data & TD_TOK_IN)
pkt->len = td_length - CRC_SIZE;
else if (pkt->info & PKT_ZLP)
pkt->len = 0;
else
pkt->len = td_length;
fhci_transaction_confirm(usb, pkt);
}
}
static void mpc52xx_psc_cw_restore_ints(struct uart_port *port)
{
out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
}
void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf)
{
out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);
}
static void uec_init_rx_parameter(uec_private_t *uec, int num_threads_rx)
{
u8 bmrx = 0;
int i;
uec_82xx_address_filtering_pram_t *p_af_pram;
/* Allocate global Rx parameter RAM page */
uec->rx_glbl_pram_offset = qe_muram_alloc(
sizeof(uec_rx_global_pram_t), UEC_RX_GLOBAL_PRAM_ALIGNMENT);
uec->p_rx_glbl_pram = (uec_rx_global_pram_t *)
qe_muram_addr(uec->rx_glbl_pram_offset);
/* Zero Global Rx parameter RAM */
memset(uec->p_rx_glbl_pram, 0, sizeof(uec_rx_global_pram_t));
/* Init global Rx parameter RAM */
/* REMODER, Extended feature mode disable, VLAN disable,
LossLess flow control disable, Receive firmware statisic disable,
Extended address parsing mode disable, One Rx queues,
Dynamic maximum/minimum frame length disable, IP checksum check
disable, IP address alignment disable
*/
out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE);
/* RQPTR */
uec->thread_dat_rx_offset = qe_muram_alloc(
num_threads_rx * sizeof(uec_thread_data_rx_t),
UEC_THREAD_DATA_ALIGNMENT);
uec->p_thread_data_rx = (uec_thread_data_rx_t *)
qe_muram_addr(uec->thread_dat_rx_offset);
out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset);
/* Type_or_Len */
out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072);
/* RxRMON base pointer, we don't need it */
out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0);
/* IntCoalescingPTR, we don't need it, no interrupt */
out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0);
/* RSTATE, global snooping, big endian, the CSB bus selected */
bmrx = BMR_INIT_VALUE;
out_8(&uec->p_rx_glbl_pram->rstate, bmrx);
/* MRBLR */
out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN);
/* RBDQPTR */
uec->rx_bd_qs_tbl_offset = qe_muram_alloc(
sizeof(uec_rx_bd_queues_entry_t) + \
sizeof(uec_rx_prefetched_bds_t),
UEC_RX_BD_QUEUES_ALIGNMENT);
uec->p_rx_bd_qs_tbl = (uec_rx_bd_queues_entry_t *)
qe_muram_addr(uec->rx_bd_qs_tbl_offset);
/* Zero it */
memset(uec->p_rx_bd_qs_tbl, 0, sizeof(uec_rx_bd_queues_entry_t) + \
sizeof(uec_rx_prefetched_bds_t));
out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset);
out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr,
(u32)uec->p_rx_bd_ring);
/* MFLR */
out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN);
/* MINFLR */
out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN);
/* MAXD1 */
out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN);
/* MAXD2 */
out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN);
/* ECAM_PTR */
out_be32(&uec->p_rx_glbl_pram->ecamptr, 0);
/* L2QT */
out_be32(&uec->p_rx_glbl_pram->l2qt, 0);
/* L3QT */
for (i = 0; i < 8; i++) {
out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0);
}
/* VLAN_TYPE */
out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100);
/* TCI */
out_be16(&uec->p_rx_glbl_pram->vlantci, 0);
/* Clear PQ2 style address filtering hash table */
p_af_pram = (uec_82xx_address_filtering_pram_t *) \
uec->p_rx_glbl_pram->addressfiltering;
p_af_pram->iaddr_h = 0;
p_af_pram->iaddr_l = 0;
p_af_pram->gaddr_h = 0;
p_af_pram->gaddr_l = 0;
}
static void mpc52xx_psc_stop_rx(struct uart_port *port)
{
port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY;
out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
}
static void cpm_uart_init_scc(struct uart_cpm_port *pinfo)
{
scc_t __iomem *scp;
scc_uart_t __iomem *sup;
pr_debug("CPM uart[%d]:init_scc\n", pinfo->port.line);
scp = pinfo->sccp;
sup = pinfo->sccup;
/* Store address */
out_be16(&pinfo->sccup->scc_genscc.scc_rbase,
(u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE);
out_be16(&pinfo->sccup->scc_genscc.scc_tbase,
(u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE);
/* Set up the uart parameters in the
* parameter ram.
*/
cpm_set_scc_fcr(sup);
out_be16(&sup->scc_genscc.scc_mrblr, pinfo->rx_fifosize);
out_be16(&sup->scc_maxidl, pinfo->rx_fifosize);
out_be16(&sup->scc_brkcr, 1);
out_be16(&sup->scc_parec, 0);
out_be16(&sup->scc_frmec, 0);
out_be16(&sup->scc_nosec, 0);
out_be16(&sup->scc_brkec, 0);
out_be16(&sup->scc_uaddr1, 0);
out_be16(&sup->scc_uaddr2, 0);
out_be16(&sup->scc_toseq, 0);
out_be16(&sup->scc_char1, 0x8000);
out_be16(&sup->scc_char2, 0x8000);
out_be16(&sup->scc_char3, 0x8000);
out_be16(&sup->scc_char4, 0x8000);
out_be16(&sup->scc_char5, 0x8000);
out_be16(&sup->scc_char6, 0x8000);
out_be16(&sup->scc_char7, 0x8000);
out_be16(&sup->scc_char8, 0x8000);
out_be16(&sup->scc_rccm, 0xc0ff);
/* Send the CPM an initialize command.
*/
cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
/* Set UART mode, 8 bit, no parity, one stop.
* Enable receive and transmit.
*/
out_be32(&scp->scc_gsmrh, 0);
out_be32(&scp->scc_gsmrl,
SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
/* Enable rx interrupts and clear all pending events. */
out_be16(&scp->scc_sccm, 0);
out_be16(&scp->scc_scce, 0xffff);
out_be16(&scp->scc_dsr, 0x7e7e);
out_be16(&scp->scc_psmr, 0x3000);
setbits32(&scp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
}
/*
* Write a string to the serial port
* Note that this is called with interrupts already disabled
*/
static void cpm_uart_early_write(struct uart_cpm_port *pinfo,
const char *string, u_int count)
{
unsigned int i;
cbd_t __iomem *bdp, *bdbase;
unsigned char *cpm_outp_addr;
/* Get the address of the host memory buffer.
*/
bdp = pinfo->tx_cur;
bdbase = pinfo->tx_bd_base;
/*
* Now, do each character. This is not as bad as it looks
* since this is a holding FIFO and not a transmitting FIFO.
* We could add the complexity of filling the entire transmit
* buffer, but we would just wait longer between accesses......
*/
for (i = 0; i < count; i++, string++) {
/* Wait for transmitter fifo to empty.
* Ready indicates output is ready, and xmt is doing
* that, not that it is ready for us to send.
*/
while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
;
/* Send the character out.
* If the buffer address is in the CPM DPRAM, don't
* convert it.
*/
cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr),
pinfo);
*cpm_outp_addr = *string;
out_be16(&bdp->cbd_datlen, 1);
setbits16(&bdp->cbd_sc, BD_SC_READY);
if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
bdp = bdbase;
else
bdp++;
/* if a LF, also do CR... */
if (*string == 10) {
while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
;
cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr),
pinfo);
*cpm_outp_addr = 13;
out_be16(&bdp->cbd_datlen, 1);
setbits16(&bdp->cbd_sc, BD_SC_READY);
if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
bdp = bdbase;
else
bdp++;
}
}
/*
* Finally, Wait for transmitter & holding register to empty
* and restore the IER
*/
while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
;
pinfo->tx_cur = bdp;
}
int misc_init_r (void)
{
unsigned char *dst;
ulong len = sizeof(fpgadata);
int status;
int index;
int i;
char *str;
unsigned long contrast0 = 0xffffffff;
dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf ("GUNZIP ERROR - must RESET board to recover\n");
do_reset (NULL, 0, 0, NULL);
}
status = fpga_boot(dst, len);
if (status != 0) {
printf("\nFPGA: Booting failed ");
switch (status) {
case ERROR_FPGA_PRG_INIT_LOW:
printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_INIT_HIGH:
printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_DONE:
printf("(Timeout: DONE not high after programming FPGA)\n ");
break;
}
/* display infos on fpgaimage */
index = 15;
for (i=0; i<4; i++) {
len = dst[index];
printf("FPGA: %s\n", &(dst[index+1]));
index += len+3;
}
putc ('\n');
/* delayed reboot */
for (i=20; i>0; i--) {
printf("Rebooting in %2d seconds \r",i);
for (index=0;index<1000;index++)
udelay(1000);
}
putc ('\n');
do_reset(NULL, 0, 0, NULL);
}
puts("FPGA: ");
/* display infos on fpgaimage */
index = 15;
for (i=0; i<4; i++) {
len = dst[index];
printf("%s ", &(dst[index+1]));
index += len+3;
}
putc ('\n');
free(dst);
/*
* Reset FPGA via FPGA_INIT pin
*/
/* setup FPGA_INIT as output */
out_be32((void *)GPIO0_TCR,
in_be32((void *)GPIO0_TCR) | FPGA_INIT);
out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) & ~FPGA_INIT); /* reset low */
udelay(1000); /* wait 1ms */
out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) | FPGA_INIT); /* reset high */
udelay(1000); /* wait 1ms */
/*
* Write Board revision into FPGA
*/
out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | (gd->board_type & 0x0003));
/*
* Setup and enable EEPROM write protection
*/
out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
/*
* Reset touch-screen controller
*/
out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_TOUCH_RST);
udelay(1000);
out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) | CONFIG_SYS_TOUCH_RST);
/*
* Enable power on PS/2 interface (with reset)
*/
out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) & ~FPGA_CTRL_PS2_PWR);
for (i=0;i<500;i++)
udelay(1000);
out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | FPGA_CTRL_PS2_PWR);
/*
* Get contrast value from environment variable
*/
str = getenv("contrast0");
if (str) {
contrast0 = simple_strtol(str, NULL, 16);
if (contrast0 > 255) {
printf("ERROR: contrast0 value too high (0x%lx)!\n",
contrast0);
contrast0 = 0xffffffff;
}
}
/*
* Init lcd interface and display logo
*/
str = getenv("bd_type");
if (strcmp(str, "ppc230") == 0) {
/*
* Switch backlight on
*/
out_be16(FPGA_CTRL,
in_be16(FPGA_CTRL) | FPGA_CTRL_VGA0_BL);
out_be16(FPGA_BL, 0x0000);
lcd_setup(1, 0);
lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
regs_13806_1024_768_8bpp,
sizeof(regs_13806_1024_768_8bpp)/sizeof(regs_13806_1024_768_8bpp[0]),
logo_bmp_1024, sizeof(logo_bmp_1024));
} else if (strcmp(str, "ppc220") == 0) {
/*
* Switch backlight on
*/
out_be16(FPGA_CTRL,
in_be16(FPGA_CTRL) & ~FPGA_CTRL_VGA0_BL);
out_be16(FPGA_BL, 0x0000);
lcd_setup(1, 0);
lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
regs_13806_640_480_16bpp,
sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
logo_bmp_640, sizeof(logo_bmp_640));
} else if (strcmp(str, "ppc215") == 0) {
/*
* Set default display contrast voltage
*/
if (contrast0 == 0xffffffff) {
out_be16(FPGA_CTR, 0x0082);
} else {
out_be16(FPGA_CTR, contrast0);
}
out_be16(FPGA_BL, 0xffff);
/*
* Switch backlight on
*/
out_be16(FPGA_CTRL,
in_be16(FPGA_CTRL) |
FPGA_CTRL_VGA0_BL |
FPGA_CTRL_VGA0_BL_MODE);
/*
* Set lcd clock (small epson)
*/
out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | LCD_CLK_06250);
udelay(100); /* wait for 100 us */
lcd_setup(0, 1);
lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
regs_13705_320_240_8bpp,
sizeof(regs_13705_320_240_8bpp)/sizeof(regs_13705_320_240_8bpp[0]),
logo_bmp_320_8bpp, sizeof(logo_bmp_320_8bpp));
} else if (strcmp(str, "ppc210") == 0) {
/*
* Set default display contrast voltage
*/
if (contrast0 == 0xffffffff) {
out_be16(FPGA_CTR, 0x0060);
} else {
out_be16(FPGA_CTR, contrast0);
}
out_be16(FPGA_BL, 0xffff);
/*
* Switch backlight on
*/
out_be16(FPGA_CTRL,
in_be16(FPGA_CTRL) |
FPGA_CTRL_VGA0_BL |
FPGA_CTRL_VGA0_BL_MODE);
/*
* Set lcd clock (small epson), enable 1-wire interface
*/
out_be16(FPGA_CTRL,
in_be16(FPGA_CTRL) |
LCD_CLK_08330 |
FPGA_CTRL_OW_ENABLE);
lcd_setup(0, 1);
lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
regs_13704_320_240_4bpp,
sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
logo_bmp_320, sizeof(logo_bmp_320));
#ifdef CONFIG_VIDEO_SM501
} else {
pci_dev_t devbusfn;
/*
* Is SM501 connected (ppc221/ppc231)?
*/
devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
if (devbusfn != -1) {
puts("VGA: SM501 with 8 MB ");
if (strcmp(str, "ppc221") == 0) {
printf("(800*600, %dbpp)\n", BPP);
out_be16(FPGA_BL, 0x002d); /* max. allowed brightness */
} else if (strcmp(str, "ppc231") == 0) {
printf("(1024*768, %dbpp)\n", BPP);
out_be16(FPGA_BL, 0x0000);
} else {
printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
return 0;
}
} else {
printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
return 0;
}
#endif /* CONFIG_VIDEO_SM501 */
}
cf_enable();
return (0);
}
/* The decrementer counts at the system (internal) clock frequency divided by
* sixteen, or external oscillator divided by four. We force the processor
* to use system clock divided by sixteen.
*/
void __init mpc8xx_calibrate_decr(void)
{
struct device_node *cpu;
cark8xx_t __iomem *clk_r1;
car8xx_t __iomem *clk_r2;
sitk8xx_t __iomem *sys_tmr1;
sit8xx_t __iomem *sys_tmr2;
int irq, virq;
clk_r1 = immr_map(im_clkrstk);
/* Unlock the SCCR. */
out_be32(&clk_r1->cark_sccrk, ~KAPWR_KEY);
out_be32(&clk_r1->cark_sccrk, KAPWR_KEY);
immr_unmap(clk_r1);
/* Force all 8xx processors to use divide by 16 processor clock. */
clk_r2 = immr_map(im_clkrst);
setbits32(&clk_r2->car_sccr, 0x02000000);
immr_unmap(clk_r2);
/* Processor frequency is MHz.
*/
ppc_proc_freq = 50000000;
if (!get_freq("clock-frequency", &ppc_proc_freq))
printk(KERN_ERR "WARNING: Estimating processor frequency "
"(not found)\n");
ppc_tb_freq = ppc_proc_freq / 16;
printk("Decrementer Frequency = 0x%lx\n", ppc_tb_freq);
/* Perform some more timer/timebase initialization. This used
* to be done elsewhere, but other changes caused it to get
* called more than once....that is a bad thing.
*
* First, unlock all of the registers we are going to modify.
* To protect them from corruption during power down, registers
* that are maintained by keep alive power are "locked". To
* modify these registers we have to write the key value to
* the key location associated with the register.
* Some boards power up with these unlocked, while others
* are locked. Writing anything (including the unlock code?)
* to the unlocked registers will lock them again. So, here
* we guarantee the registers are locked, then we unlock them
* for our use.
*/
sys_tmr1 = immr_map(im_sitk);
out_be32(&sys_tmr1->sitk_tbscrk, ~KAPWR_KEY);
out_be32(&sys_tmr1->sitk_rtcsck, ~KAPWR_KEY);
out_be32(&sys_tmr1->sitk_tbk, ~KAPWR_KEY);
out_be32(&sys_tmr1->sitk_tbscrk, KAPWR_KEY);
out_be32(&sys_tmr1->sitk_rtcsck, KAPWR_KEY);
out_be32(&sys_tmr1->sitk_tbk, KAPWR_KEY);
immr_unmap(sys_tmr1);
init_internal_rtc();
/* Enabling the decrementer also enables the timebase interrupts
* (or from the other point of view, to get decrementer interrupts
* we have to enable the timebase). The decrementer interrupt
* is wired into the vector table, nothing to do here for that.
*/
cpu = of_find_node_by_type(NULL, "cpu");
virq= irq_of_parse_and_map(cpu, 0);
irq = virq_to_hw(virq);
sys_tmr2 = immr_map(im_sit);
out_be16(&sys_tmr2->sit_tbscr, ((1 << (7 - (irq/2))) << 8) |
(TBSCR_TBF | TBSCR_TBE));
immr_unmap(sys_tmr2);
if (setup_irq(virq, &tbint_irqaction))
panic("Could not allocate timer IRQ!");
}
void cyclicInt(void *ptr)
{
out_be16((void *)0xf03000e8, 0x0800); /* ack int */
counter++;
}
int board_early_init_f (void)
{
int index, len, i;
int status;
#ifdef FPGA_DEBUG
/* set up serial port with default baudrate */
(void) get_clocks ();
gd->baudrate = CONFIG_BAUDRATE;
serial_init ();
console_init_f ();
#endif
/*
* Boot onboard FPGA
*/
/* first try 40er image */
gd->board_type = 40;
status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
if (status != 0) {
/* try xl30er image */
gd->board_type = 30;
status = fpga_boot ((unsigned char *) fpgadata_xl30, sizeof (fpgadata_xl30));
if (status != 0) {
/* booting FPGA failed */
#ifndef FPGA_DEBUG
/* set up serial port with default baudrate */
(void) get_clocks ();
gd->baudrate = CONFIG_BAUDRATE;
serial_init ();
console_init_f ();
#endif
printf ("\nFPGA: Booting failed ");
switch (status) {
case ERROR_FPGA_PRG_INIT_LOW:
printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_INIT_HIGH:
printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_DONE:
printf ("(Timeout: DONE not high after programming FPGA)\n ");
break;
}
/* display infos on fpgaimage */
index = 15;
for (i = 0; i < 4; i++) {
len = fpgadata[index];
printf ("FPGA: %s\n", &(fpgadata[index + 1]));
index += len + 3;
}
putc ('\n');
/* delayed reboot */
for (i = 20; i > 0; i--) {
printf ("Rebooting in %2d seconds \r", i);
for (index = 0; index < 1000; index++)
udelay (1000);
}
putc ('\n');
do_reset (NULL, 0, 0, NULL);
}
}
/*
* IRQ 0-15 405GP internally generated; active high; level sensitive
* IRQ 16 405GP internally generated; active low; level sensitive
* IRQ 17-24 RESERVED
* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
* IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
* IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
* IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
* IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
out_be16((void *)0xf03000ec, 0x0fff); /* enable interrupts in fpga */
return 0;
}
int do_anatest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
short val;
int i;
int volt;
struct io *out;
struct io *in;
out = (struct io *)0xf0300090;
in = (struct io *)0xf0300000;
i = simple_strtol (argv[1], NULL, 10);
volt = 0;
printf("Setting Channel %d to %dV...\n", i, volt);
out_be16((void *)&(out[i].val), (volt * 0x7fff) / 10);
udelay(10000);
val = in_be16((void *)&(in[i*2].val));
printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
(val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
((volt * 0x7fff) / 40) + ERROR_DELTA);
return -1;
}
val = in_be16((void *)&(in[i*2+1].val));
printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
(val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
((volt * 0x7fff) / 40) + ERROR_DELTA);
return -1;
}
volt = 5;
printf("Setting Channel %d to %dV...\n", i, volt);
out_be16((void *)&(out[i].val), (volt * 0x7fff) / 10);
udelay(10000);
val = in_be16((void *)&(in[i*2].val));
printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
(val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
((volt * 0x7fff) / 40) + ERROR_DELTA);
return -1;
}
val = in_be16((void *)&(in[i*2+1].val));
printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
(val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
((volt * 0x7fff) / 40) + ERROR_DELTA);
return -1;
}
volt = 10;
printf("Setting Channel %d to %dV...\n", i, volt);
out_be16((void *)&(out[i].val), (volt * 0x7fff) / 10);
udelay(10000);
val = in_be16((void *)&(in[i*2].val));
printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
(val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
((volt * 0x7fff) / 40) + ERROR_DELTA);
return -1;
}
val = in_be16((void *)&(in[i*2+1].val));
printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
(val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
((volt * 0x7fff) / 40) + ERROR_DELTA);
return -1;
}
printf("Channel %d OK!\n", i);
return 0;
}
/*
* Upload a microcode to the I-RAM at a specific address.
*
* See docs/README.qe_firmware for information on QE microcode uploading.
*
* Currently, only version 1 is supported, so the 'version' field must be
* set to 1.
*
* The SOC model and revision are not validated, they are only displayed for
* informational purposes.
*
* 'calc_size' is the calculated size, in bytes, of the firmware structure and
* all of the microcode structures, minus the CRC.
*
* 'length' is the size that the structure says it is, including the CRC.
*/
int u_qe_upload_firmware(const struct qe_firmware *firmware)
{
unsigned int i;
unsigned int j;
u32 crc;
size_t calc_size = sizeof(struct qe_firmware);
size_t length;
const struct qe_header *hdr;
#ifdef CONFIG_DEEP_SLEEP
#ifdef CONFIG_LS102XA
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
#else
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
#endif
if (!firmware) {
printf("Invalid address\n");
return -EINVAL;
}
hdr = &firmware->header;
length = be32_to_cpu(hdr->length);
/* Check the magic */
if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
(hdr->magic[2] != 'F')) {
printf("Not a microcode\n");
#ifdef CONFIG_DEEP_SLEEP
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
#endif
return -EPERM;
}
/* Check the version */
if (hdr->version != 1) {
printf("Unsupported version\n");
return -EPERM;
}
/* Validate some of the fields */
if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
printf("Invalid data\n");
return -EINVAL;
}
/* Validate the length and check if there's a CRC */
calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
for (i = 0; i < firmware->count; i++)
/*
* For situations where the second RISC uses the same microcode
* as the first, the 'code_offset' and 'count' fields will be
* zero, so it's okay to add those.
*/
calc_size += sizeof(u32) *
be32_to_cpu(firmware->microcode[i].count);
/* Validate the length */
if (length != calc_size + sizeof(u32)) {
printf("Invalid length\n");
return -EPERM;
}
/*
* Validate the CRC. We would normally call crc32_no_comp(), but that
* function isn't available unless you turn on JFFS support.
*/
crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) {
printf("Firmware CRC is invalid\n");
return -EIO;
}
/*
* If the microcode calls for it, split the I-RAM.
*/
if (!firmware->split) {
out_be16(&qe_immr->cp.cercr,
in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);
}
if (firmware->soc.model)
printf("Firmware '%s' for %u V%u.%u\n",
firmware->id, be16_to_cpu(firmware->soc.model),
firmware->soc.major, firmware->soc.minor);
else
printf("Firmware '%s'\n", firmware->id);
/* Loop through each microcode. */
for (i = 0; i < firmware->count; i++) {
const struct qe_microcode *ucode = &firmware->microcode[i];
/* Upload a microcode if it's present */
if (ucode->code_offset)
qe_upload_microcode(firmware, ucode);
/* Program the traps for this processor */
for (j = 0; j < 16; j++) {
u32 trap = be32_to_cpu(ucode->traps[j]);
if (trap)
out_be32(&qe_immr->rsp[i].tibcr[j], trap);
}
/* Enable traps */
out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
}
return 0;
}
/*
* Submitting a data frame to a specified endpoint of a USB device
* The frame is put in the driver's transmit queue for this endpoint
*
* Arguments:
* usb A pointer to the USB structure
* pkt A pointer to the user frame structure
* trans_type Transaction tyep - IN,OUT or SETUP
* dest_addr Device address - 0~127
* dest_ep Endpoint number of the device - 0~16
* trans_mode Pipe type - ISO,Interrupt,bulk or control
* dest_speed USB speed - Low speed or FULL speed
* data_toggle Data sequence toggle - 0 or 1
*/
u32 fhci_host_transaction(struct fhci_usb *usb,
struct packet *pkt,
enum fhci_ta_type trans_type,
u8 dest_addr,
u8 dest_ep,
enum fhci_tf_mode trans_mode,
enum fhci_speed dest_speed, u8 data_toggle)
{
struct endpoint *ep = usb->ep0;
struct usb_td __iomem *td;
u16 extra_data;
u16 td_status;
fhci_usb_disable_interrupt(usb);
/* start from the next BD that should be filled */
td = ep->empty_td;
td_status = in_be16(&td->status);
if (td_status & TD_R && in_be16(&td->length)) {
/* if the TD is not free */
fhci_usb_enable_interrupt(usb);
return -1;
}
/* get the next TD in the ring */
ep->empty_td = next_bd(ep->td_base, ep->empty_td, td_status);
fhci_usb_enable_interrupt(usb);
pkt->priv_data = td;
out_be32(&td->buf_ptr, virt_to_phys(pkt->data));
/* sets up transaction parameters - addr,endp,dir,and type */
extra_data = (dest_ep << TD_ENDP_SHIFT) | dest_addr;
switch (trans_type) {
case FHCI_TA_IN:
extra_data |= TD_TOK_IN;
break;
case FHCI_TA_OUT:
extra_data |= TD_TOK_OUT;
break;
case FHCI_TA_SETUP:
extra_data |= TD_TOK_SETUP;
break;
}
if (trans_mode == FHCI_TF_ISO)
extra_data |= TD_ISO;
out_be16(&td->extra, extra_data);
/* sets up the buffer descriptor */
td_status = ((td_status & TD_W) | TD_R | TD_L | TD_I | TD_CNF);
if (!(pkt->info & PKT_NO_CRC))
td_status |= TD_TC;
switch (trans_type) {
case FHCI_TA_IN:
if (data_toggle)
pkt->info |= PKT_PID_DATA1;
else
pkt->info |= PKT_PID_DATA0;
break;
default:
if (data_toggle) {
td_status |= TD_PID_DATA1;
pkt->info |= PKT_PID_DATA1;
} else {
td_status |= TD_PID_DATA0;
pkt->info |= PKT_PID_DATA0;
}
break;
}
if ((dest_speed == FHCI_LOW_SPEED) &&
(usb->port_status == FHCI_PORT_FULL))
td_status |= TD_LSP;
out_be16(&td->status, td_status);
/* set up buffer length */
if (trans_type == FHCI_TA_IN)
out_be16(&td->length, pkt->len + CRC_SIZE);
else
out_be16(&td->length, pkt->len);
/* put the frame to the confirmation queue */
cq_put(&ep->conf_frame_Q, pkt);
if (cq_howmany(&ep->conf_frame_Q) == 1)
out_8(&usb->fhci->regs->usb_comm, USB_CMD_STR_FIFO);
return 0;
}
static void cpm_uart_set_termios(struct uart_port *port,
struct ktermios *termios,
struct ktermios *old)
{
int baud;
unsigned long flags;
u16 cval, scval, prev_mode;
int bits, sbits;
struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
smc_t __iomem *smcp = pinfo->smcp;
scc_t __iomem *sccp = pinfo->sccp;
pr_debug("CPM uart[%d]:set_termios\n", port->line);
baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
if (baud <= HW_BUF_SPD_THRESHOLD ||
(pinfo->port.state && pinfo->port.state->port.tty->low_latency))
pinfo->rx_fifosize = 1;
else
pinfo->rx_fifosize = RX_BUF_SIZE;
/* Character length programmed into the mode register is the
* sum of: 1 start bit, number of data bits, 0 or 1 parity bit,
* 1 or 2 stop bits, minus 1.
* The value 'bits' counts this for us.
*/
cval = 0;
scval = 0;
/* byte size */
switch (termios->c_cflag & CSIZE) {
case CS5:
bits = 5;
break;
case CS6:
bits = 6;
break;
case CS7:
bits = 7;
break;
case CS8:
bits = 8;
break;
/* Never happens, but GCC is too dumb to figure it out */
default:
bits = 8;
break;
}
sbits = bits - 5;
if (termios->c_cflag & CSTOPB) {
cval |= SMCMR_SL; /* Two stops */
scval |= SCU_PSMR_SL;
bits++;
}
if (termios->c_cflag & PARENB) {
cval |= SMCMR_PEN;
scval |= SCU_PSMR_PEN;
bits++;
if (!(termios->c_cflag & PARODD)) {
cval |= SMCMR_PM_EVEN;
scval |= (SCU_PSMR_REVP | SCU_PSMR_TEVP);
}
}
/*
* Update the timeout
*/
uart_update_timeout(port, termios->c_cflag, baud);
/*
* Set up parity check flag
*/
#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
port->read_status_mask = (BD_SC_EMPTY | BD_SC_OV);
if (termios->c_iflag & INPCK)
port->read_status_mask |= BD_SC_FR | BD_SC_PR;
if ((termios->c_iflag & BRKINT) || (termios->c_iflag & PARMRK))
port->read_status_mask |= BD_SC_BR;
/*
* Characters to ignore
*/
port->ignore_status_mask = 0;
if (termios->c_iflag & IGNPAR)
port->ignore_status_mask |= BD_SC_PR | BD_SC_FR;
if (termios->c_iflag & IGNBRK) {
port->ignore_status_mask |= BD_SC_BR;
/*
* If we're ignore parity and break indicators, ignore
* overruns too. (For real raw support).
*/
if (termios->c_iflag & IGNPAR)
port->ignore_status_mask |= BD_SC_OV;
}
/*
* !!! ignore all characters if CREAD is not set
*/
if ((termios->c_cflag & CREAD) == 0)
port->read_status_mask &= ~BD_SC_EMPTY;
spin_lock_irqsave(&port->lock, flags);
/* Start bit has not been added (so don't, because we would just
* subtract it later), and we need to add one for the number of
* stops bits (there is always at least one).
*/
bits++;
if (IS_SMC(pinfo)) {
/*
* MRBLR can be changed while an SMC/SCC is operating only
* if it is done in a single bus cycle with one 16-bit move
* (not two 8-bit bus cycles back-to-back). This occurs when
* the cp shifts control to the next RxBD, so the change does
* not take effect immediately. To guarantee the exact RxBD
* on which the change occurs, change MRBLR only while the
* SMC/SCC receiver is disabled.
*/
out_be16(&pinfo->smcup->smc_mrblr, pinfo->rx_fifosize);
/* Set the mode register. We want to keep a copy of the
* enables, because we want to put them back if they were
* present.
*/
prev_mode = in_be16(&smcp->smc_smcmr) & (SMCMR_REN | SMCMR_TEN);
/* Output in *one* operation, so we don't interrupt RX/TX if they
* were already enabled. */
out_be16(&smcp->smc_smcmr, smcr_mk_clen(bits) | cval |
SMCMR_SM_UART | prev_mode);
} else {
out_be16(&pinfo->sccup->scc_genscc.scc_mrblr, pinfo->rx_fifosize);
out_be16(&sccp->scc_psmr, (sbits << 12) | scval);
}
if (pinfo->clk)
clk_set_rate(pinfo->clk, baud);
else
cpm_set_brg(pinfo->brg - 1, baud);
spin_unlock_irqrestore(&port->lock, flags);
}
int misc_init_r(void)
{
u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
u16 *fpga_ctrl2 =(u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL2);
u8 *duart0_mcr = (u8 *)(DUART0_BA + 4);
u8 *duart1_mcr = (u8 *)(DUART1_BA + 4);
unsigned char *dst;
ulong len = sizeof(fpgadata);
int status;
int index;
int i;
unsigned long CPC0_CR0Reg;
char *str;
uchar *logo_addr;
ulong logo_size;
ushort minb, maxb;
int result;
/*
* Setup GPIO pins (CS6+CS7 as GPIO)
*/
CPC0_CR0Reg = mfdcr(CPC0_CR0);
mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf("GUNZIP ERROR - must RESET board to recover\n");
do_reset(NULL, 0, 0, NULL);
}
status = fpga_boot(dst, len);
if (status != 0) {
printf("\nFPGA: Booting failed ");
switch (status) {
case ERROR_FPGA_PRG_INIT_LOW:
printf("(Timeout: "
"INIT not low after asserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_INIT_HIGH:
printf("(Timeout: "
"INIT not high after deasserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_DONE:
printf("(Timeout: "
"DONE not high after programming FPGA)\n ");
break;
}
/* display infos on fpgaimage */
index = 15;
for (i = 0; i < 4; i++) {
len = dst[index];
printf("FPGA: %s\n", &(dst[index+1]));
index += len + 3;
}
putc('\n');
/* delayed reboot */
for (i = 20; i > 0; i--) {
printf("Rebooting in %2d seconds \r",i);
for (index = 0; index < 1000; index++)
udelay(1000);
}
putc('\n');
do_reset(NULL, 0, 0, NULL);
}
/* restore gpio/cs settings */
mtdcr(CPC0_CR0, CPC0_CR0Reg);
puts("FPGA: ");
/* display infos on fpgaimage */
index = 15;
for (i = 0; i < 4; i++) {
len = dst[index];
printf("%s ", &(dst[index + 1]));
index += len + 3;
}
putc('\n');
free(dst);
/*
* Reset FPGA via FPGA_DATA pin
*/
SET_FPGA(FPGA_PRG | FPGA_CLK);
udelay(1000); /* wait 1ms */
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
udelay(1000); /* wait 1ms */
/*
* Write board revision in FPGA
*/
out_be16(fpga_ctrl2,
(in_be16(fpga_ctrl2) & 0xfff0) | (gd->board_type & 0x000f));
/*
* Enable power on PS/2 interface (with reset)
*/
out_be16(fpga_mode, in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_PS2_RESET);
for (i=0;i<100;i++)
udelay(1000);
udelay(1000);
out_be16(fpga_mode, in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_PS2_RESET);
/*
* Enable interrupts in exar duart mcr[3]
*/
out_8(duart0_mcr, 0x08);
out_8(duart1_mcr, 0x08);
/*
* Init lcd interface and display logo
*/
str = getenv("splashimage");
if (str) {
logo_addr = (uchar *)simple_strtoul(str, NULL, 16);
logo_size = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
} else {
logo_addr = logo_bmp;
logo_size = sizeof(logo_bmp);
}
if (gd->board_type >= 6) {
result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
(uchar *)CONFIG_SYS_LCD_BIG_MEM,
regs_13505_640_480_16bpp,
sizeof(regs_13505_640_480_16bpp) /
sizeof(regs_13505_640_480_16bpp[0]),
logo_addr, logo_size);
if (result && str) {
/* retry with internal image */
logo_addr = logo_bmp;
logo_size = sizeof(logo_bmp);
lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
(uchar *)CONFIG_SYS_LCD_BIG_MEM,
regs_13505_640_480_16bpp,
sizeof(regs_13505_640_480_16bpp) /
sizeof(regs_13505_640_480_16bpp[0]),
logo_addr, logo_size);
}
} else {
result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
(uchar *)CONFIG_SYS_LCD_BIG_MEM,
regs_13806_640_480_16bpp,
sizeof(regs_13806_640_480_16bpp) /
sizeof(regs_13806_640_480_16bpp[0]),
logo_addr, logo_size);
if (result && str) {
/* retry with internal image */
logo_addr = logo_bmp;
logo_size = sizeof(logo_bmp);
lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
(uchar *)CONFIG_SYS_LCD_BIG_MEM,
regs_13806_640_480_16bpp,
sizeof(regs_13806_640_480_16bpp) /
sizeof(regs_13806_640_480_16bpp[0]),
logo_addr, logo_size);
}
}
/*
* Reset microcontroller and setup backlight PWM controller
*/
out_be16(fpga_mode, in_be16(fpga_mode) | 0x0014);
for (i=0;i<10;i++)
udelay(1000);
out_be16(fpga_mode, in_be16(fpga_mode) | 0x001c);
minb = 0;
maxb = 0xff;
str = getenv("lcdbl");
if (str) {
minb = (ushort)simple_strtoul(str, &str, 16) & 0x00ff;
if (str && (*str=',')) {
str++;
maxb = (ushort)simple_strtoul(str, NULL, 16) & 0x00ff;
} else
minb = 0;
out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMIN), minb);
out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMAX), maxb);
printf("LCDBL: min=0x%02x, max=0x%02x\n", minb, maxb);
}
out_be16((u16 *)(FUJI_BASE + LCDBL_PWM), 0xff);
/*
* fix environment for field updated units
*/
if (getenv("altbootcmd") == NULL) {
setenv("usb_load", CONFIG_SYS_USB_LOAD_COMMAND);
setenv("usbargs", CONFIG_SYS_USB_ARGS);
setenv("bootcmd", CONFIG_BOOTCOMMAND);
setenv("usb_self", CONFIG_SYS_USB_SELF_COMMAND);
setenv("bootlimit", CONFIG_SYS_BOOTLIMIT);
setenv("altbootcmd", CONFIG_SYS_ALT_BOOTCOMMAND);
saveenv();
}
return (0);
}
/*
* Transmit characters, refill buffer descriptor, if possible
*/
static int cpm_uart_tx_pump(struct uart_port *port)
{
cbd_t __iomem *bdp;
u8 *p;
int count;
struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
struct circ_buf *xmit = &port->state->xmit;
/* Handle xon/xoff */
if (port->x_char) {
/* Pick next descriptor and fill from buffer */
bdp = pinfo->tx_cur;
p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
*p++ = port->x_char;
out_be16(&bdp->cbd_datlen, 1);
setbits16(&bdp->cbd_sc, BD_SC_READY);
/* Get next BD. */
if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
bdp = pinfo->tx_bd_base;
else
bdp++;
pinfo->tx_cur = bdp;
port->icount.tx++;
port->x_char = 0;
return 1;
}
if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
cpm_uart_stop_tx(port);
return 0;
}
/* Pick next descriptor and fill from buffer */
bdp = pinfo->tx_cur;
while (!(in_be16(&bdp->cbd_sc) & BD_SC_READY) &&
xmit->tail != xmit->head) {
count = 0;
p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
while (count < pinfo->tx_fifosize) {
*p++ = xmit->buf[xmit->tail];
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
port->icount.tx++;
count++;
if (xmit->head == xmit->tail)
break;
}
out_be16(&bdp->cbd_datlen, count);
setbits16(&bdp->cbd_sc, BD_SC_READY);
/* Get next BD. */
if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
bdp = pinfo->tx_bd_base;
else
bdp++;
}
pinfo->tx_cur = bdp;
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
if (uart_circ_empty(xmit)) {
cpm_uart_stop_tx(port);
return 0;
}
return 1;
}
void cpu_init_f(void)
{
scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
#ifndef CONFIG_WATCHDOG
wdog_t *wdog = (wdog_t *) MMAP_WDOG;
/* watchdog is enabled by default - disable the watchdog */
out_be16(&wdog->cr, 0);
#endif
out_be32(&scm1->mpr0, 0x77777777);
out_be32(&scm2->pacra, 0);
out_be32(&scm2->pacrb, 0);
out_be32(&scm2->pacrc, 0);
out_be32(&scm2->pacrd, 0);
out_be32(&scm2->pacre, 0);
out_be32(&scm2->pacrf, 0);
out_be32(&scm2->pacrg, 0);
out_be32(&scm1->pacrh, 0);
/* Port configuration */
out_8(&gpio->par_cs, 0);
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
&& defined(CONFIG_SYS_CS0_CTRL))
out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
#endif
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
&& defined(CONFIG_SYS_CS1_CTRL))
/* Latch chipselect */
setbits_8(&gpio->par_cs, GPIO_PAR_CS1);
out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
#endif
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
&& defined(CONFIG_SYS_CS2_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS2);
out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
#endif
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
&& defined(CONFIG_SYS_CS3_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS3);
out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
&& defined(CONFIG_SYS_CS4_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS4);
out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
#endif
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
&& defined(CONFIG_SYS_CS5_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS5);
out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif
#ifdef CONFIG_SYS_I2C_FSL
out_8(&gpio->par_feci2c,
GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
#endif
icache_enable();
}
static void cpm_uart_init_smc(struct uart_cpm_port *pinfo)
{
smc_t __iomem *sp;
smc_uart_t __iomem *up;
pr_debug("CPM uart[%d]:init_smc\n", pinfo->port.line);
sp = pinfo->smcp;
up = pinfo->smcup;
/* Store address */
out_be16(&pinfo->smcup->smc_rbase,
(u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE);
out_be16(&pinfo->smcup->smc_tbase,
(u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE);
/*
* In case SMC1 is being relocated...
*/
#if defined (CONFIG_I2C_SPI_SMC1_UCODE_PATCH)
out_be16(&up->smc_rbptr, in_be16(&pinfo->smcup->smc_rbase));
out_be16(&up->smc_tbptr, in_be16(&pinfo->smcup->smc_tbase));
out_be32(&up->smc_rstate, 0);
out_be32(&up->smc_tstate, 0);
out_be16(&up->smc_brkcr, 1); /* number of break chars */
out_be16(&up->smc_brkec, 0);
#endif
/* Set up the uart parameters in the
* parameter ram.
*/
cpm_set_smc_fcr(up);
/* Using idle character time requires some additional tuning. */
out_be16(&up->smc_mrblr, pinfo->rx_fifosize);
out_be16(&up->smc_maxidl, pinfo->rx_fifosize);
out_be16(&up->smc_brklen, 0);
out_be16(&up->smc_brkec, 0);
out_be16(&up->smc_brkcr, 1);
cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
/* Set UART mode, 8 bit, no parity, one stop.
* Enable receive and transmit.
*/
out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART);
/* Enable only rx interrupts clear all pending events. */
out_8(&sp->smc_smcm, 0);
out_8(&sp->smc_smce, 0xff);
setbits16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
}
static int __devinit
bcom_engine_init(void)
{
int task;
phys_addr_t tdt_pa, ctx_pa, var_pa, fdt_pa;
unsigned int tdt_size, ctx_size, var_size, fdt_size;
/* Allocate & clear SRAM zones for FDT, TDTs, contexts and vars/incs */
tdt_size = BCOM_MAX_TASKS * sizeof(struct bcom_tdt);
ctx_size = BCOM_MAX_TASKS * BCOM_CTX_SIZE;
var_size = BCOM_MAX_TASKS * (BCOM_VAR_SIZE + BCOM_INC_SIZE);
fdt_size = BCOM_FDT_SIZE;
bcom_eng->tdt = bcom_sram_alloc(tdt_size, sizeof(u32), &tdt_pa);
bcom_eng->ctx = bcom_sram_alloc(ctx_size, BCOM_CTX_ALIGN, &ctx_pa);
bcom_eng->var = bcom_sram_alloc(var_size, BCOM_VAR_ALIGN, &var_pa);
bcom_eng->fdt = bcom_sram_alloc(fdt_size, BCOM_FDT_ALIGN, &fdt_pa);
if (!bcom_eng->tdt || !bcom_eng->ctx || !bcom_eng->var || !bcom_eng->fdt) {
printk(KERN_ERR "DMA: SRAM alloc failed in engine init !\n");
bcom_sram_free(bcom_eng->tdt);
bcom_sram_free(bcom_eng->ctx);
bcom_sram_free(bcom_eng->var);
bcom_sram_free(bcom_eng->fdt);
return -ENOMEM;
}
memset(bcom_eng->tdt, 0x00, tdt_size);
memset(bcom_eng->ctx, 0x00, ctx_size);
memset(bcom_eng->var, 0x00, var_size);
memset(bcom_eng->fdt, 0x00, fdt_size);
/* Copy the FDT for the EU#3 */
memcpy(&bcom_eng->fdt[48], fdt_ops, sizeof(fdt_ops));
/* Initialize Task base structure */
for (task=0; task<BCOM_MAX_TASKS; task++)
{
out_be16(&bcom_eng->regs->tcr[task], 0);
out_8(&bcom_eng->regs->ipr[task], 0);
bcom_eng->tdt[task].context = ctx_pa;
bcom_eng->tdt[task].var = var_pa;
bcom_eng->tdt[task].fdt = fdt_pa;
var_pa += BCOM_VAR_SIZE + BCOM_INC_SIZE;
ctx_pa += BCOM_CTX_SIZE;
}
out_be32(&bcom_eng->regs->taskBar, tdt_pa);
/* Init 'always' initiator */
out_8(&bcom_eng->regs->ipr[BCOM_INITIATOR_ALWAYS], BCOM_IPR_ALWAYS);
/* Disable COMM Bus Prefetch on the original 5200; it's broken */
if ((mfspr(SPRN_SVR) & MPC5200_SVR_MASK) == MPC5200_SVR)
bcom_disable_prefetch();
/* Init lock */
spin_lock_init(&bcom_eng->lock);
return 0;
}
static void uec_init_tx_parameter(uec_private_t *uec, int num_threads_tx)
{
uec_info_t *uec_info;
u32 end_bd;
u8 bmrx = 0;
int i;
uec_info = uec->uec_info;
/* Alloc global Tx parameter RAM page */
uec->tx_glbl_pram_offset = qe_muram_alloc(
sizeof(uec_tx_global_pram_t),
UEC_TX_GLOBAL_PRAM_ALIGNMENT);
uec->p_tx_glbl_pram = (uec_tx_global_pram_t *)
qe_muram_addr(uec->tx_glbl_pram_offset);
/* Zero the global Tx prameter RAM */
memset(uec->p_tx_glbl_pram, 0, sizeof(uec_tx_global_pram_t));
/* Init global Tx parameter RAM */
/* TEMODER, RMON statistics disable, one Tx queue */
out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE);
/* SQPTR */
uec->send_q_mem_reg_offset = qe_muram_alloc(
sizeof(uec_send_queue_qd_t),
UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
uec->p_send_q_mem_reg = (uec_send_queue_mem_region_t *)
qe_muram_addr(uec->send_q_mem_reg_offset);
out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset);
/* Setup the table with TxBDs ring */
end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1)
* SIZEOFBD;
out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base,
(u32)(uec->p_tx_bd_ring));
out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address,
end_bd);
/* Scheduler Base Pointer, we have only one Tx queue, no need it */
out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0);
/* TxRMON Base Pointer, TxRMON disable, we don't need it */
out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0);
/* TSTATE, global snooping, big endian, the CSB bus selected */
bmrx = BMR_INIT_VALUE;
out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT));
/* IPH_Offset */
for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++) {
out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0);
}
/* VTAG table */
for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++) {
out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0);
}
/* TQPTR */
uec->thread_dat_tx_offset = qe_muram_alloc(
num_threads_tx * sizeof(uec_thread_data_tx_t) +
32 *(num_threads_tx == 1), UEC_THREAD_DATA_ALIGNMENT);
uec->p_thread_data_tx = (uec_thread_data_tx_t *)
qe_muram_addr(uec->thread_dat_tx_offset);
out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset);
}
phys_size_t initdram(int board_type)
{
sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
/* Enable SDRAM */
out_be16(&gpio_reg->par_sdram, 0x3FF);
/* Set up chip select */
out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE);
out_be32(&sdp->sdbmr0, MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V);
/* Set up timing */
out_be32(&sdp->sdcfg1, 0x83711630);
out_be32(&sdp->sdcfg2, 0x46770000);
/* Enable clock */
out_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE);
/* Set precharge */
setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
/* Dummy write to start SDRAM */
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Send LEMR */
setbits_be32(&sdp->sdmr,
MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_AD(0x0) |
MCF_SDRAMC_SDMR_CMD);
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Send LMR */
out_be32(&sdp->sdmr, 0x058d0000);
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop sending commands */
clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
/* Set precharge */
setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop manual precharge, send 2 IREF */
clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF);
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
out_be32(&sdp->sdmr, 0x018d0000);
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop sending commands */
clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN);
/* Turn on auto refresh, lock SDMR */
out_be32(&sdp->sdcr,
MCF_SDRAMC_SDCR_CKE
| MCF_SDRAMC_SDCR_REF
| MCF_SDRAMC_SDCR_MUX(1)
/* 1 added to round up */
| MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
| MCF_SDRAMC_SDCR_DQS_OE(0x3));
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
};
void pci_mcf547x_8x_init(struct pci_controller *hose)
{
pci_t *pci = (pci_t *) MMAP_PCI;
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Port configuration */
out_be16(&gpio->par_pcibg,
GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) |
GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) |
GPIO_PAR_PCIBG_PCIBG4(3));
out_be16(&gpio->par_pcibr,
GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) |
GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) |
GPIO_PAR_PCIBR_PCIBR4(3));
/* Assert reset bit */
setbits_be32(&pci->gscr, PCI_GSCR_PR);
out_be32(&pci->tcr1, PCI_TCR1_P);
/* Initiator windows */
out_be32(&pci->iw0btar,
CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16));
out_be32(&pci->iw1btar,
CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16));
out_be32(&pci->iw2btar,
CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16));
out_be32(&pci->iwcr,
PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO);
out_be32(&pci->icr, 0);
/* Enable bus master and mem access */
out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M);
/* Cache line size and master latency */
out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xf8));
out_be32(&pci->cr2, 0);
#ifdef CONFIG_SYS_PCI_BAR0
out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0));
out_be32(&pci->tbatr0a, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN);
#endif
#ifdef CONFIG_SYS_PCI_BAR1
out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1));
out_be32(&pci->tbatr1a, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN);
#endif
/* Deassert reset bit */
clrbits_be32(&pci->gscr, PCI_GSCR_PR);
udelay(1000);
/* Enable PCI bus master support */
hose->first_busno = 0;
hose->last_busno = 0xff;
pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS,
CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS,
CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS,
CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
hose->region_count = 3;
hose->cfg_addr = &(pci->car);
hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS;
pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
pci_write_cfg_dword);
/* Hose scan */
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
}
static void ace_out_be16(struct ace_device *ace, int reg, u16 val)
{
out_be16(ace->baseaddr + reg, val);
}
static void mpc52xx_psc_cw_disable_ints(struct uart_port *port)
{
out_be16(&PSC(port)->mpc52xx_psc_imr, 0);
}
static int __devinit hpfb_init_one(unsigned long phys_base,
unsigned long virt_base)
{
unsigned long fboff, fb_width, fb_height, fb_start;
fb_regs = virt_base;
fboff = (in_8(fb_regs + HPFB_FBOMSB) << 8) | in_8(fb_regs + HPFB_FBOLSB);
fb_info.fix.smem_start = (in_8(fb_regs + fboff) << 16);
if (phys_base >= DIOII_BASE) {
fb_info.fix.smem_start += phys_base;
}
if (DIO_SECID(fb_regs) != DIO_ID2_TOPCAT) {
/* */
while (in_be16(fb_regs+0x4800) & 1)
;
out_be16(fb_regs+0x4800, 0); /* */
out_be16(fb_regs+0x4510, 0); /* */
out_be16(fb_regs+0x4512, 0); /* */
out_be16(fb_regs+0x4514, 0); /* */
out_be16(fb_regs+0x4516, 0); /* */
out_be16(fb_regs+0x4206, 0x90); /* */
out_be16(fb_regs+0x60a2, 0); /* */
out_be16(fb_regs+0x60bc, 0); /* */
}
/*
*/
fb_width = (in_8(fb_regs + HPFB_FBWMSB) << 8) | in_8(fb_regs + HPFB_FBWLSB);
fb_info.fix.line_length = fb_width;
fb_height = (in_8(fb_regs + HPFB_FBHMSB) << 8) | in_8(fb_regs + HPFB_FBHLSB);
fb_info.fix.smem_len = fb_width * fb_height;
fb_start = (unsigned long)ioremap_writethrough(fb_info.fix.smem_start,
fb_info.fix.smem_len);
hpfb_defined.xres = (in_8(fb_regs + HPFB_DWMSB) << 8) | in_8(fb_regs + HPFB_DWLSB);
hpfb_defined.yres = (in_8(fb_regs + HPFB_DHMSB) << 8) | in_8(fb_regs + HPFB_DHLSB);
hpfb_defined.xres_virtual = hpfb_defined.xres;
hpfb_defined.yres_virtual = hpfb_defined.yres;
hpfb_defined.bits_per_pixel = in_8(fb_regs + HPFB_NUMPLANES);
printk(KERN_INFO "hpfb: framebuffer at 0x%lx, mapped to 0x%lx, size %dk\n",
fb_info.fix.smem_start, fb_start, fb_info.fix.smem_len/1024);
printk(KERN_INFO "hpfb: mode is %dx%dx%d, linelength=%d\n",
hpfb_defined.xres, hpfb_defined.yres, hpfb_defined.bits_per_pixel, fb_info.fix.line_length);
/*
*/
out_8(fb_regs + TC_WEN, 0xff);
out_8(fb_regs + TC_PRR, RR_COPY);
out_8(fb_regs + TC_FBEN, 0xff);
out_8(fb_start, 0xff);
fb_bitmask = in_8(fb_start);
out_8(fb_start, 0);
/*
*/
out_8(fb_regs + TC_WEN, fb_bitmask);
out_8(fb_regs + TC_PRR, RR_COPY);
out_8(fb_regs + TC_REN, fb_bitmask);
out_8(fb_regs + TC_FBEN, fb_bitmask);
/*
*/
topcat_blit(0, 0, 0, 0, fb_width, fb_height, RR_CLEAR);
/*
*/
if (DIO_SECID(fb_regs) == DIO_ID2_TOPCAT)
strcat(fb_info.fix.id, "Topcat");
else
strcat(fb_info.fix.id, "Catseye");
fb_info.fbops = &hpfb_ops;
fb_info.flags = FBINFO_DEFAULT;
fb_info.var = hpfb_defined;
fb_info.screen_base = (char *)fb_start;
fb_alloc_cmap(&fb_info.cmap, 1 << hpfb_defined.bits_per_pixel, 0);
if (register_framebuffer(&fb_info) < 0) {
fb_dealloc_cmap(&fb_info.cmap);
iounmap(fb_info.screen_base);
fb_info.screen_base = NULL;
return 1;
}
printk(KERN_INFO "fb%d: %s frame buffer device\n",
fb_info.node, fb_info.fix.id);
return 0;
}
int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** uccf_ret)
{
struct ucc_fast_private *uccf;
struct ucc_fast __iomem *uf_regs;
u32 gumr;
int ret;
if (!uf_info)
return -EINVAL;
/* check if the UCC port number is in range. */
if ((uf_info->ucc_num < 0) || (uf_info->ucc_num > UCC_MAX_NUM - 1)) {
printk(KERN_ERR "%s: illegal UCC number\n", __func__);
return -EINVAL;
}
/* Check that 'max_rx_buf_length' is properly aligned (4). */
if (uf_info->max_rx_buf_length & (UCC_FAST_MRBLR_ALIGNMENT - 1)) {
printk(KERN_ERR "%s: max_rx_buf_length not aligned\n",
__func__);
return -EINVAL;
}
/* Validate Virtual Fifo register values */
if (uf_info->urfs < UCC_FAST_URFS_MIN_VAL) {
printk(KERN_ERR "%s: urfs is too small\n", __func__);
return -EINVAL;
}
if (uf_info->urfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
printk(KERN_ERR "%s: urfs is not aligned\n", __func__);
return -EINVAL;
}
if (uf_info->urfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
printk(KERN_ERR "%s: urfet is not aligned.\n", __func__);
return -EINVAL;
}
if (uf_info->urfset & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
printk(KERN_ERR "%s: urfset is not aligned\n", __func__);
return -EINVAL;
}
if (uf_info->utfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
printk(KERN_ERR "%s: utfs is not aligned\n", __func__);
return -EINVAL;
}
if (uf_info->utfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
printk(KERN_ERR "%s: utfet is not aligned\n", __func__);
return -EINVAL;
}
if (uf_info->utftt & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
printk(KERN_ERR "%s: utftt is not aligned\n", __func__);
return -EINVAL;
}
uccf = kzalloc(sizeof(struct ucc_fast_private), GFP_KERNEL);
if (!uccf) {
printk(KERN_ERR "%s: Cannot allocate private data\n",
__func__);
return -ENOMEM;
}
/* Fill fast UCC structure */
uccf->uf_info = uf_info;
/* Set the PHY base address */
uccf->uf_regs = ioremap(uf_info->regs, sizeof(struct ucc_fast));
if (uccf->uf_regs == NULL) {
printk(KERN_ERR "%s: Cannot map UCC registers\n", __func__);
kfree(uccf);
return -ENOMEM;
}
uccf->enabled_tx = 0;
uccf->enabled_rx = 0;
uccf->stopped_tx = 0;
uccf->stopped_rx = 0;
uf_regs = uccf->uf_regs;
uccf->p_ucce = &uf_regs->ucce;
uccf->p_uccm = &uf_regs->uccm;
#ifdef CONFIG_UGETH_TX_ON_DEMAND
uccf->p_utodr = &uf_regs->utodr;
#endif
#ifdef STATISTICS
uccf->tx_frames = 0;
uccf->rx_frames = 0;
uccf->rx_discarded = 0;
#endif /* STATISTICS */
/* Set UCC to fast type */
ret = ucc_set_type(uf_info->ucc_num, UCC_SPEED_TYPE_FAST);
if (ret) {
printk(KERN_ERR "%s: cannot set UCC type\n", __func__);
ucc_fast_free(uccf);
return ret;
}
uccf->mrblr = uf_info->max_rx_buf_length;
/* Set GUMR */
/* For more details see the hardware spec. */
gumr = uf_info->ttx_trx;
if (uf_info->tci)
gumr |= UCC_FAST_GUMR_TCI;
if (uf_info->cdp)
gumr |= UCC_FAST_GUMR_CDP;
if (uf_info->ctsp)
gumr |= UCC_FAST_GUMR_CTSP;
if (uf_info->cds)
gumr |= UCC_FAST_GUMR_CDS;
if (uf_info->ctss)
gumr |= UCC_FAST_GUMR_CTSS;
if (uf_info->txsy)
gumr |= UCC_FAST_GUMR_TXSY;
if (uf_info->rsyn)
gumr |= UCC_FAST_GUMR_RSYN;
gumr |= uf_info->synl;
if (uf_info->rtsm)
gumr |= UCC_FAST_GUMR_RTSM;
gumr |= uf_info->renc;
if (uf_info->revd)
gumr |= UCC_FAST_GUMR_REVD;
gumr |= uf_info->tenc;
gumr |= uf_info->tcrc;
gumr |= uf_info->mode;
out_be32(&uf_regs->gumr, gumr);
/* Allocate memory for Tx Virtual Fifo */
uccf->ucc_fast_tx_virtual_fifo_base_offset =
qe_muram_alloc(uf_info->utfs, UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
if (IS_ERR_VALUE(uccf->ucc_fast_tx_virtual_fifo_base_offset)) {
printk(KERN_ERR "%s: cannot allocate MURAM for TX FIFO\n",
__func__);
uccf->ucc_fast_tx_virtual_fifo_base_offset = 0;
ucc_fast_free(uccf);
return -ENOMEM;
}
/* Allocate memory for Rx Virtual Fifo */
uccf->ucc_fast_rx_virtual_fifo_base_offset =
qe_muram_alloc(uf_info->urfs +
UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR,
UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
if (IS_ERR_VALUE(uccf->ucc_fast_rx_virtual_fifo_base_offset)) {
printk(KERN_ERR "%s: cannot allocate MURAM for RX FIFO\n",
__func__);
uccf->ucc_fast_rx_virtual_fifo_base_offset = 0;
ucc_fast_free(uccf);
return -ENOMEM;
}
/* Set Virtual Fifo registers */
out_be16(&uf_regs->urfs, uf_info->urfs);
out_be16(&uf_regs->urfet, uf_info->urfet);
out_be16(&uf_regs->urfset, uf_info->urfset);
out_be16(&uf_regs->utfs, uf_info->utfs);
out_be16(&uf_regs->utfet, uf_info->utfet);
out_be16(&uf_regs->utftt, uf_info->utftt);
/* utfb, urfb are offsets from MURAM base */
out_be32(&uf_regs->utfb, uccf->ucc_fast_tx_virtual_fifo_base_offset);
out_be32(&uf_regs->urfb, uccf->ucc_fast_rx_virtual_fifo_base_offset);
/* Mux clocking */
/* Grant Support */
ucc_set_qe_mux_grant(uf_info->ucc_num, uf_info->grant_support);
/* Breakpoint Support */
ucc_set_qe_mux_bkpt(uf_info->ucc_num, uf_info->brkpt_support);
/* Set Tsa or NMSI mode. */
ucc_set_qe_mux_tsa(uf_info->ucc_num, uf_info->tsa);
/* If NMSI (not Tsa), set Tx and Rx clock. */
if (!uf_info->tsa) {
/* Rx clock routing */
if ((uf_info->rx_clock != QE_CLK_NONE) &&
ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->rx_clock,
COMM_DIR_RX)) {
printk(KERN_ERR "%s: illegal value for RX clock\n",
__func__);
ucc_fast_free(uccf);
return -EINVAL;
}
/* Tx clock routing */
if ((uf_info->tx_clock != QE_CLK_NONE) &&
ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->tx_clock,
COMM_DIR_TX)) {
printk(KERN_ERR "%s: illegal value for TX clock\n",
__func__);
ucc_fast_free(uccf);
return -EINVAL;
}
}
/* Set interrupt mask register at UCC level. */
out_be32(&uf_regs->uccm, uf_info->uccm_mask);
/* First, clear anything pending at UCC level,
* otherwise, old garbage may come through
* as soon as the dam is opened. */
/* Writing '1' clears */
out_be32(&uf_regs->ucce, 0xffffffff);
*uccf_ret = uccf;
return 0;
}
static int __init cpm_uart_console_setup(struct console *co, char *options)
{
int baud = 38400;
int bits = 8;
int parity = 'n';
int flow = 'n';
int ret;
struct uart_cpm_port *pinfo;
struct uart_port *port;
struct device_node *np = NULL;
int i = 0;
if (co->index >= UART_NR) {
printk(KERN_ERR "cpm_uart: console index %d too high\n",
co->index);
return -ENODEV;
}
do {
np = of_find_node_by_type(np, "serial");
if (!np)
return -ENODEV;
if (!of_device_is_compatible(np, "fsl,cpm1-smc-uart") &&
!of_device_is_compatible(np, "fsl,cpm1-scc-uart") &&
!of_device_is_compatible(np, "fsl,cpm2-smc-uart") &&
!of_device_is_compatible(np, "fsl,cpm2-scc-uart"))
i--;
} while (i++ != co->index);
pinfo = &cpm_uart_ports[co->index];
pinfo->flags |= FLAG_CONSOLE;
port = &pinfo->port;
ret = cpm_uart_init_port(np, pinfo);
of_node_put(np);
if (ret)
return ret;
if (options) {
uart_parse_options(options, &baud, &parity, &bits, &flow);
} else {
if ((baud = uart_baudrate()) == -1)
baud = 9600;
}
if (IS_SMC(pinfo)) {
out_be16(&pinfo->smcup->smc_brkcr, 0);
cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX);
clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
} else {
out_be16(&pinfo->sccup->scc_brkcr, 0);
cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX);
clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
}
ret = cpm_uart_allocbuf(pinfo, 1);
if (ret)
return ret;
cpm_uart_initbd(pinfo);
if (IS_SMC(pinfo))
cpm_uart_init_smc(pinfo);
else
cpm_uart_init_scc(pinfo);
uart_set_options(port, co, baud, parity, bits, flow);
cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX);
return 0;
}
static int __devinit hpfb_init_one(unsigned long phys_base,
unsigned long virt_base)
{
unsigned long fboff, fb_width, fb_height, fb_start;
fb_regs = virt_base;
fboff = (in_8(fb_regs + HPFB_FBOMSB) << 8) | in_8(fb_regs + HPFB_FBOLSB);
fb_info.fix.smem_start = (in_8(fb_regs + fboff) << 16);
if (phys_base >= DIOII_BASE) {
fb_info.fix.smem_start += phys_base;
}
if (DIO_SECID(fb_regs) != DIO_ID2_TOPCAT) {
/* This is the magic incantation the HP X server uses to make Catseye boards work. */
while (in_be16(fb_regs+0x4800) & 1)
;
out_be16(fb_regs+0x4800, 0); /* Catseye status */
out_be16(fb_regs+0x4510, 0); /* VB */
out_be16(fb_regs+0x4512, 0); /* TCNTRL */
out_be16(fb_regs+0x4514, 0); /* ACNTRL */
out_be16(fb_regs+0x4516, 0); /* PNCNTRL */
out_be16(fb_regs+0x4206, 0x90); /* RUG Command/Status */
out_be16(fb_regs+0x60a2, 0); /* Overlay Mask */
out_be16(fb_regs+0x60bc, 0); /* Ram Select */
}
/*
* Fill in the available video resolution
*/
fb_width = (in_8(fb_regs + HPFB_FBWMSB) << 8) | in_8(fb_regs + HPFB_FBWLSB);
fb_info.fix.line_length = fb_width;
fb_height = (in_8(fb_regs + HPFB_FBHMSB) << 8) | in_8(fb_regs + HPFB_FBHLSB);
fb_info.fix.smem_len = fb_width * fb_height;
fb_start = (unsigned long)ioremap_writethrough(fb_info.fix.smem_start,
fb_info.fix.smem_len);
hpfb_defined.xres = (in_8(fb_regs + HPFB_DWMSB) << 8) | in_8(fb_regs + HPFB_DWLSB);
hpfb_defined.yres = (in_8(fb_regs + HPFB_DHMSB) << 8) | in_8(fb_regs + HPFB_DHLSB);
hpfb_defined.xres_virtual = hpfb_defined.xres;
hpfb_defined.yres_virtual = hpfb_defined.yres;
hpfb_defined.bits_per_pixel = in_8(fb_regs + HPFB_NUMPLANES);
printk(KERN_INFO "hpfb: framebuffer at 0x%lx, mapped to 0x%lx, size %dk\n",
fb_info.fix.smem_start, fb_start, fb_info.fix.smem_len/1024);
printk(KERN_INFO "hpfb: mode is %dx%dx%d, linelength=%d\n",
hpfb_defined.xres, hpfb_defined.yres, hpfb_defined.bits_per_pixel, fb_info.fix.line_length);
/*
* Give the hardware a bit of a prod and work out how many bits per
* pixel are supported.
*/
out_8(fb_regs + TC_WEN, 0xff);
out_8(fb_regs + TC_PRR, RR_COPY);
out_8(fb_regs + TC_FBEN, 0xff);
out_8(fb_start, 0xff);
fb_bitmask = in_8(fb_start);
out_8(fb_start, 0);
/*
* Enable reading/writing of all the planes.
*/
out_8(fb_regs + TC_WEN, fb_bitmask);
out_8(fb_regs + TC_PRR, RR_COPY);
out_8(fb_regs + TC_REN, fb_bitmask);
out_8(fb_regs + TC_FBEN, fb_bitmask);
/*
* Clear the screen.
*/
topcat_blit(0, 0, 0, 0, fb_width, fb_height, RR_CLEAR);
/*
* Let there be consoles..
*/
if (DIO_SECID(fb_regs) == DIO_ID2_TOPCAT)
strcat(fb_info.fix.id, "Topcat");
else
strcat(fb_info.fix.id, "Catseye");
fb_info.fbops = &hpfb_ops;
fb_info.flags = FBINFO_DEFAULT;
fb_info.var = hpfb_defined;
fb_info.screen_base = (char *)fb_start;
fb_alloc_cmap(&fb_info.cmap, 1 << hpfb_defined.bits_per_pixel, 0);
if (register_framebuffer(&fb_info) < 0) {
fb_dealloc_cmap(&fb_info.cmap);
iounmap(fb_info.screen_base);
fb_info.screen_base = NULL;
return 1;
}
printk(KERN_INFO "fb%d: %s frame buffer device\n",
fb_info.node, fb_info.fix.id);
return 0;
}
/*
* create the endpoint structure
*
* arguments:
* usb A pointer to the data structure of the USB
* data_mem The data memory partition(BUS)
* ring_len TD ring length
*/
u32 fhci_create_ep(struct fhci_usb *usb, enum fhci_mem_alloc data_mem,
u32 ring_len)
{
struct endpoint *ep;
struct usb_td __iomem *td;
unsigned long ep_offset;
char *err_for = "enpoint PRAM";
int ep_mem_size;
u32 i;
/* we need at least 3 TDs in the ring */
if (!(ring_len > 2)) {
fhci_err(usb->fhci, "illegal TD ring length parameters\n");
return -EINVAL;
}
ep = kzalloc(sizeof(*ep), GFP_KERNEL);
if (!ep)
return -ENOMEM;
ep_mem_size = ring_len * sizeof(*td) + sizeof(struct fhci_ep_pram);
ep_offset = cpm_muram_alloc(ep_mem_size, 32);
if (IS_ERR_VALUE(ep_offset))
goto err;
ep->td_base = cpm_muram_addr(ep_offset);
/* zero all queue pointers */
if (cq_new(&ep->conf_frame_Q, ring_len + 2) ||
cq_new(&ep->empty_frame_Q, ring_len + 2) ||
cq_new(&ep->dummy_packets_Q, ring_len + 2)) {
err_for = "frame_queues";
goto err;
}
for (i = 0; i < (ring_len + 1); i++) {
struct packet *pkt;
u8 *buff;
pkt = kmalloc(sizeof(*pkt), GFP_KERNEL);
if (!pkt) {
err_for = "frame";
goto err;
}
buff = kmalloc(1028 * sizeof(*buff), GFP_KERNEL);
if (!buff) {
kfree(pkt);
err_for = "buffer";
goto err;
}
cq_put(&ep->empty_frame_Q, pkt);
cq_put(&ep->dummy_packets_Q, buff);
}
/* we put the endpoint parameter RAM right behind the TD ring */
ep->ep_pram_ptr = (void __iomem *)ep->td_base + sizeof(*td) * ring_len;
ep->conf_td = ep->td_base;
ep->empty_td = ep->td_base;
ep->already_pushed_dummy_bd = false;
/* initialize tds */
td = ep->td_base;
for (i = 0; i < ring_len; i++) {
out_be32(&td->buf_ptr, 0);
out_be16(&td->status, 0);
out_be16(&td->length, 0);
out_be16(&td->extra, 0);
td++;
}
td--;
out_be16(&td->status, TD_W); /* for last TD set Wrap bit */
out_be16(&td->length, 0);
/* endpoint structure has been created */
usb->ep0 = ep;
return 0;
err:
fhci_ep0_free(usb);
kfree(ep);
fhci_err(usb->fhci, "no memory for the %s\n", err_for);
return -ENOMEM;
}
