static int mb862xx_i2c_do_address(struct i2c_adapter *adap, int addr) { struct mb862xxfb_par *par = adap->algo_data; outreg(i2c, GC_I2C_DAR, addr); outreg(i2c, GC_I2C_CCR, I2C_CLOCK_AND_ENABLE); outreg(i2c, GC_I2C_BCR, par->i2c_rs ? I2C_REPEATED_START : I2C_START); if (!mb862xx_i2c_wait_event(adap)) return -EIO; par->i2c_rs = !(inreg(i2c, GC_I2C_BSR) & I2C_LRB); return par->i2c_rs; }
static int mb862xxfb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, unsigned transp, struct fb_info *info) { struct mb862xxfb_par *par = info->par; unsigned int val; switch (info->fix.visual) { case FB_VISUAL_TRUECOLOR: if (regno < 16) { val = chan_to_field(red, &info->var.red); val |= chan_to_field(green, &info->var.green); val |= chan_to_field(blue, &info->var.blue); par->pseudo_palette[regno] = val; } break; case FB_VISUAL_PSEUDOCOLOR: if (regno < 256) { val = (red >> 8) << 16; val |= (green >> 8) << 8; val |= blue >> 8; outreg(disp, GC_L0PAL0 + (regno * 4), val); } break; default: return 1; /* unsupported type */ }
// output an operand bool idaapi outop(op_t &op) { switch ( op.type ) { // register case o_reg: outreg(op.reg); break; // immediate case o_imm: if ( (op.specflag1 & OP_IMM_BIT) == 0 ) out_symbol('#'); OutValue(op, OOFW_IMM); break; // data / code memory address case o_near: case o_mem: outaddr(op); break; // displ case o_displ: outdispl(); break; // ignore void operands case o_void: break; default: INTERR(10024); } return 1; }
/****************************** Routine: Description: Set the baud rate. ******************************/ void serial_set(int channel, unsigned long baud) { unsigned char sav_lcr; /* * Enable access to the divisor latches by setting DLAB in LCR. * */ sav_lcr = inreg(channel, LCR); #if 0 /* * Set baud rate */ outreg(channel, LCR, LCR_DLAB | sav_lcr); // outreg(DLL,(XTAL/(16*2*(baud))-2)); outreg(channel, DLL, XTAL / (16 * baud)); // outreg(DLM,(XTAL/(16*2*(baud))-2)>>8); outreg(channel, DLM, (XTAL / (16 * baud)) >> 8); #else /* * Note: Set baud rate, hardcoded here for rate of 115200 * since became unsure of above "buad rate" algorithm (??). */ outreg(channel, LCR, 0x83); outreg(channel, DLM, 0x00); // See note above outreg(channel, DLL, 0x02); // See note above. outreg(channel, LCR, 0x03); #endif /* * Restore line control register */ outreg(channel, LCR, sav_lcr); }
//---------------------------------------------------------------------- bool idaapi outop(op_t &x) { ea_t ea; if ( x.type == o_imm ) out_symbol('#'); char buf[MAXSTR]; switch ( x.type ) { case o_void: return 0; case o_imm: OutValue(x, OOFS_IFSIGN|OOFW_IMM); break; case o_reg: outreg(x.reg); break; case o_mem: // no break; case o_near: { ea = calc_mem(x); if ( ea == cmd.ea+cmd.size ) out_ip_rel(cmd.size); else if ( !out_name_expr(x, ea, x.addr) ) out_bad_address(x.addr); } break; case o_phrase: { qsnprintf(buf, sizeof(buf), "%%%c%" FMT_EA "x", 'a' + x.reg, x.value); ea = calc_data_mem(x, as + x.reg); if ( ( ea != BADADDR ) && ( ( x.reg != SR3 ) || ( x.value < 6 ) ) ) { out_line(buf, COLOR_AUTOCMT); out_symbol(' '); out_address(ea, x); } else out_line(buf, COLOR_REG); } break; default: interr("out"); break; } return 1; }
static int mb862xx_i2c_read_byte(struct i2c_adapter *adap, u8 *byte, int last) { struct mb862xxfb_par *par = adap->algo_data; outreg(i2c, GC_I2C_BCR, I2C_START | (last ? 0 : I2C_ACK)); if (!mb862xx_i2c_wait_event(adap)) return 0; *byte = inreg(i2c, GC_I2C_DAR); return 1; }
/****************************** Routine: Description: Initialize the device driver. ******************************/ void serial_init(int channel) { /* * Configure active port, (CHANNELOFFSET already set.) * * Set 8 bits, 1 stop bit, no parity. * * LCR<7> 0 divisor latch access bit * LCR<6> 0 break control (1=send break) * LCR<5> 0 stick parity (0=space, 1=mark) * LCR<4> 0 parity even (0=odd, 1=even) * LCR<3> 0 parity enable (1=enabled) * LCR<2> 0 # stop bits (0=1, 1=1.5) * LCR<1:0> 11 bits per character(00=5, 01=6, 10=7, 11=8) */ outreg(channel, LCR, 0x3); outreg(channel, FCR, FIFO_ENABLE); /* Enable the FIFO */ outreg(channel, IER, INT_ENABLE); /* Enable appropriate interrupts */ }
//---------------------------------------------------------------------- static void out_reglist(int reg, int cnt) { int bit = 1; int delayed = -1; int first = 1; for ( int i=0; i <= cnt; i++,bit<<=1 ) { if ( (reg & bit) == 0 ) { if ( delayed >= 0 ) { if ( !first ) out_symbol(','); if ( delayed == (i-1) ) { outreg(delayed); } else if ( delayed == (i-2) ) { outreg(delayed); out_symbol(','); outreg(delayed+1); } else { outreg(delayed); out_symbol('-'); outreg(i-1); } delayed = -1; first = 0; } } else { if ( delayed < 0 ) delayed = i; } } }
static void init_uart () { outreg(IER,0x02); /* Enable Tx Empty interrupt - should generate an interrupt since Tx is empty to begin with */ }
static void disable_uart_ints () { outreg(IER,0); /* Make the uart shut up */ }
/* Transmit a character. */ void serial_putc(int c) { while ((inreg(LSR) & LSR_THRE) == 0) ; outreg(DataOut, c); }
// output an operand bool idaapi outop(op_t &x) { switch ( x.type ) { // register case o_reg: outreg(x.reg); break; // immediate case o_imm: { const ioport_t *port = find_sym(x.value); // this immediate is represented in the .cfg file if ( port != NULL ) { // output the port name instead of the numeric value out_line(port->name, COLOR_IMPNAME); } // otherwise, simply print the value else { out_symbol('#'); OutValue(x, OOFW_IMM|OOF_SIGNED); } } break; // displ @(imm, reg) case o_displ: out_symbol('@'); out_symbol('('); OutValue(x, OOF_SIGNED | OOF_ADDR | OOFW_32); out_symbol(','); OutChar(' '); outreg(x.reg); out_symbol(')'); break; // address case o_near: if ( !out_name_expr(x, toEA(cmd.cs, x.addr), x.addr) ) OutValue(x, OOF_ADDR | OOF_NUMBER | OOFS_NOSIGN | OOFW_32); break; // phrase case o_phrase: switch ( x.specflag1 ) { // @R case fRI: out_symbol('@'); if ( isDefArg(uFlag, x.n) ) { out_symbol('('); OutValue(x, 0); // will print 0 out_symbol(','); OutChar(' '); outreg(x.reg); out_symbol(')'); } else { outreg(x.reg); } break; // @R+ case fRIBA: out_symbol('@'); outreg(x.reg); out_symbol('+'); break; // @+R case fRIAA: out_symbol('@'); out_symbol('+'); outreg(x.reg); break; // @-R case fRIAS: out_symbol('@'); out_symbol('-'); outreg(x.reg); break; } break; } return 1; }
//---------------------------------------------------------------------- bool outop(op_t &x) { ea_t ea; char buf[MAXSTR]; if ( x.type == o_imm ) out_symbol('#'); switch ( x.type ) { case o_void: return 0; case o_imm: if ( x.amode & amode_signed ) OutValue(x, OOF_SIGNED|OOFW_IMM); else OutValue(x, OOFS_IFSIGN|OOFW_IMM); break; case o_reg: outreg(x.reg); break; case o_mem: // no break; ea = calc_mem(x); if ( ea != BADADDR ) out_address(ea, x); else { out_tagon(COLOR_ERROR); OutValue(x, OOFW_IMM|OOF_ADDR|OOFW_16); out_tagoff(COLOR_ERROR); } break; case o_near: { ea_t ea = calc_mem(x); // xmem ioports if ( x.amode & (amode_x) && out_port_address(x.addr) ) { char nbuf[MAXSTR]; const char *pnam = find_port(x.addr); const char *name = get_true_name(BADADDR, ea, nbuf, sizeof(nbuf)); if ( name == NULL || strcmp(name, pnam) != 0 ) set_name(ea, pnam); break; } if ( ea == cmd.ea+cmd.size ) out_ip_rel(cmd.size); else if ( !out_name_expr(x, ea, x.addr) ) out_bad_address(x.addr); } break; case o_phrase: { if ( x.phtype < 4 ) { qsnprintf(buf, sizeof(buf), formats[x.phtype], x.phrase); out_colored_register_line(buf); } if ( x.phtype == 4 ) { out_symbol('('); outreg(x.reg); out_symbol(')'); } } break; case o_local: { out_colored_register_line(formats2[x.phtype]); OutValue(x, OOF_SIGNED|OOF_ADDR); if ( x.phtype == 0 ) out_symbol(')'); break; } case o_textphrase: { char buf[MAXSTR]; switch ( x.textphtype ) { case text_swap: out_line(swap_formats[x.phrase], COLOR_REG); break; case text_banke: int comma; char r0[10], r1[10], r4[10], cfgi[10]; comma = 0; r0[0]=r1[0]=r4[0]=cfgi[0]='\0'; if ( x.phrase & 0x01 ) //cfgi { qsnprintf(cfgi, sizeof(cfgi), "cfgi"); comma = 1; } if ( x.phrase & 0x02 ) //r4 { qsnprintf(r4, sizeof(r4), "r4%s", (comma?", ":"")); comma = 1; } if ( x.phrase & 0x04 ) //r1 { qsnprintf(r1, sizeof(r1), "r1%s", (comma?", ":"")); comma = 1; } if ( x.phrase & 0x08 ) //r0 qsnprintf(r0, sizeof(r0), "r0%s", (comma?", ":"")); qsnprintf(buf, sizeof(buf), "%s%s%s%s", r0, r1, r4, cfgi ); out_line(buf, COLOR_REG); break; case text_cntx: out_symbol( (x.phrase ? 'r': 's') ); break; case text_dmod: if ( x.phrase ) qsnprintf(buf, sizeof(buf), " no modulo"); else qsnprintf(buf, sizeof(buf), " modulo"); out_line(buf, COLOR_REG); break; case text_eu: qsnprintf(buf, sizeof(buf), " eu"); out_line(buf, COLOR_REG); break; } } break; default: interr("out"); break; } return 1; }
//---------------------------------------------------------------------- bool outop(op_t &x) { switch ( x.type ) { case o_void: return 0; case o_reg: outreg(x.reg); break; case o_imm: out_symbol('#'); OutValue(x, OOFS_IFSIGN|OOFW_IMM); break; case o_displ: // o_displ Short Direct Indexed ld A,($10,X) 00..1FE + 1 // o_displ Long Direct Indexed ld A,($1000,X) 0000..FFFF + 2 out_symbol('('); OutValue(x, OOFS_IFSIGN |OOF_ADDR |((cmd.auxpref & aux_16) ? OOFW_16 : OOFW_8)); out_symbol(','); outreg(x.reg); out_symbol(')'); break; case o_phrase: out_symbol('('); outreg(x.reg); out_symbol(')'); break; case o_mem: // o_mem Short Direct ld A,$10 00..FF + 1 // o_mem Long Direct ld A,$1000 0000..FFFF + 2 // o_mem Short Indirect ld A,[$10] 00..FF 00..FF byte + 2 // o_mem Long Indirect ld A,[$10.w] 0000..FFFF 00..FF word + 2 // o_mem Short Indirect Indexed ld A,([$10],X) 00..1FE 00..FF byte + 2 // o_mem Long Indirect Indexed ld A,([$10.w],X) 0000..FFFF 00..FF word + 2 // o_mem Relative Indirect jrne [$10] PC+/-127 00..FF byte + 2 // o_mem Bit Direct bset $10,#7 00..FF + 1 // o_mem Bit Indirect bset [$10],#7 00..FF 00..FF byte + 2 // o_mem Bit Direct Relative btjt $10,#7,skip 00..FF + 2 // o_mem Bit Indirect Relative btjt [$10],#7,skip 00..FF 00..FF byte + 3 if ( cmd.auxpref & aux_index ) out_symbol('('); if ( cmd.auxpref & aux_indir ) out_symbol('['); outmem(x, calc_mem(x.addr)); if ( cmd.auxpref & aux_long ) out_symbol('.'); if ( cmd.auxpref & aux_long ) out_symbol('w'); if ( cmd.auxpref & aux_indir ) out_symbol(']'); if ( cmd.auxpref & aux_index ) { out_symbol(','); outreg(x.reg); out_symbol(')'); } break; case o_near: outmem(x, calc_mem(x.addr)); break; default: interr("out"); break; } return 1; }
//---------------------------------------------------------------------- bool outop(op_t &x) { switch ( x.type ) { case o_void: return 0; case o_reg: outreg(x.reg); break; case o_reglist: out_symbol('('); out_reglist(x.reg, 8); out_symbol(')'); break; case o_imm: out_symbol('#'); OutValue(x, calc_opimm_flags()); out_sizer(x); break; case o_mem: out_symbol('@'); case o_near: case o_far: { ea_t ea = calc_mem(x); if ( !out_name_expr(x, ea, BADADDR) ) out_bad_address(x.addr); out_sizer(x); } break; case o_phrase: if ( x.phtype == ph_normal ) { bool outdisp = isOff(uFlag,x.n) || isStkvar(uFlag,x.n) || isEnum(uFlag,x.n) || isStroff(uFlag,x.n); if ( outdisp ) goto OUTDISP; } out_symbol('@'); if ( x.phtype == ph_pre ) out_symbol('-'); outreg(x.phrase); if ( x.phtype == ph_post ) out_symbol('+'); break; case o_displ: OUTDISP: out_symbol('@'); out_symbol('('); OutValue(x, calc_opdispl_flags()); out_sizer(x); out_symbol(','); outreg(x.reg); out_symbol(')'); break; default: interr("out"); break; } return 1; }
/****************************** Routine: Description: Transmit a character. ******************************/ void serial_putc(int channel, int c) { while ((inreg(channel, LSR) & LSR_THRE) == 0); outreg(channel, THR, c); }