/* start measurement (CONVERT_T) for all sensors if input id==NULL
or for single sensor. then id is the rom-code */
uint8_t DS18X20_start_meas( uint8_t with_power_extern, uint8_t id[])
{
ow_reset(); //**
if( ow_input_pin_state() ) { // only send if bus is "idle" = high
ow_command( DS18X20_CONVERT_T, id );
if (with_power_extern != DS18X20_POWER_EXTERN)
ow_parasite_enable();
return DS18X20_OK;
}
else {
return DS18X20_START_FAIL;
}
}
/* start measurement (CONVERT_T) for all sensors if input id==NULL
or for single sensor. then id is the rom-code */
uint8_t DS18X20_start_meas(uint8_t with_power_extern, uint8_t id[])
{
ow_reset(); //**
if (ow_input_pin_state()) { // only send if bus is "idle" = high
ow_command(DS18X20_CONVERT_T, id);
if (with_power_extern != DS18X20_POWER_EXTERN)
ow_parasite_enable();
return DS18X20_OK;
} else {
#ifdef DS18X20_VERBOSE
printf_P(PSTR("DS18X20_start_meas: Short Circuit !\r"));
#endif
return DS18X20_START_FAIL;
}
}
uint8_t DS18X20_copy_scratchpad( uint8_t with_power_extern,
uint8_t id[] )
{
ow_reset(); //**
if( ow_input_pin_state() ) { // only send if bus is "idle" = high
ow_command( DS18X20_COPY_SCRATCHPAD, id );
if (with_power_extern != DS18X20_POWER_EXTERN)
ow_parasite_enable();
_delay_ms(10); // wait for 10 ms
if (with_power_extern != DS18X20_POWER_EXTERN)
ow_parasite_disable();
return DS18X20_OK;
}
else {
return DS18X20_START_FAIL;
}
}
uint8_t DS18X20_copy_scratchpad(uint8_t with_power_extern,
uint8_t id[])
{
ow_reset(); //**
if (ow_input_pin_state()) { // only send if bus is "idle" = high
ow_command(DS18X20_COPY_SCRATCHPAD, id);
if (with_power_extern != DS18X20_POWER_EXTERN)
ow_parasite_enable();
_delay_ms(DS18X20_COPYSP_DELAY); // wait for 10 ms
if (with_power_extern != DS18X20_POWER_EXTERN)
ow_parasite_disable();
return DS18X20_OK;
} else {
#ifdef DS18X20_VERBOSE
printf_P(PSTR("DS18X20_copy_scratchpad: Short Circuit !\r"));
#endif
return DS18X20_START_FAIL;
}
}
/* Timing issue when using runtime-bus-selection (!OW_ONE_BUS):
The master should sample at the end of the 15-slot after initiating
the read-time-slot. The variable bus-settings need more
cycles than the constant ones so the delays had to be shortened
to achive a 15uS overall delay
Setting/clearing a bit in I/O Register needs 1 cyle in OW_ONE_BUS
but around 14 cyles in configureable bus (us-Delay is 4 cyles per uS) */
static uint8_t ow_bit_io_intern( uint8_t b, uint8_t with_parasite_enable )
{
/*ATOMIC_BLOCK(ATOMIC_RESTORESTATE) */{
#if OW_USE_INTERNAL_PULLUP
OW_OUT_LOW();
#endif
OW_DIR_OUT(); // drive bus low
_delay_us(2); // T_INT > 1usec accoding to timing-diagramm
if ( b ) {
OW_DIR_IN(); // to write "1" release bus, resistor pulls high
#if OW_USE_INTERNAL_PULLUP
OW_OUT_HIGH();
#endif
}
// "Output data from the DS18B20 is valid for 15usec after the falling
// edge that initiated the read time slot. Therefore, the master must
// release the bus and then sample the bus state within 15ussec from
// the start of the slot."
_delay_us(15-2-OW_CONF_DELAYOFFSET);
if( OW_GET_IN() == 0 ) {
b = 0; // sample at end of read-timeslot
}
_delay_us(60-15-2+OW_CONF_DELAYOFFSET);
#if OW_USE_INTERNAL_PULLUP
OW_OUT_HIGH();
#endif
OW_DIR_IN();
if ( with_parasite_enable ) {
ow_parasite_enable();
}
} /* ATOMIC_BLOCK */
_delay_us(OW_RECOVERY_TIME); // may be increased for longer wires
return b;
}
