static void soc_init(void *data) { struct global_nvs_t *gnvs; /* Save VBT info and mapping */ if (locate_vbt(&vbt_rdev) != CB_ERR) vbt = rdev_mmap_full(&vbt_rdev); /* Snapshot the current GPIO IRQ polarities. FSP is setting a * default policy that doesn't honor boards' requirements. */ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); fsp_silicon_init(); /* Restore GPIO IRQ polarities back to previous settings. */ itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); /* override 'enabled' setting in device tree if needed */ pcie_override_devicetree_after_silicon_init(); /* * Keep the P2SB device visible so it and the other devices are * visible in coreboot for driver support and PCI resource allocation. * There is a UPD setting for this, but it's more consistent to use * hide and unhide symmetrically. */ p2sb_unhide(); /* Allocate ACPI NVS in CBMEM */ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); }
static void pch_disable_heci(void) { struct pcr_sbi_msg msg = { .pid = PID_CSME0, .offset = 0, .opcode = PCR_WRITE, .is_posted = false, .fast_byte_enable = CSME0_FBE, .bar = CSME0_BAR, .fid = CSME0_FID }; /* Bit 0: Set to make HECI#1 Function disable */ uint32_t data32 = 1; uint8_t response; int status; /* unhide p2sb device */ p2sb_unhide(); /* Send SBI command to make HECI#1 function disable */ status = pcr_execute_sideband_msg(&msg, &data32, &response); if (status && response) printk(BIOS_ERR, "Fail to make CSME function disable\n"); /* Ensure to Lock SBI interface after this command */ p2sb_disable_sideband_access(); /* hide p2sb device */ p2sb_hide(); } /* * Specific SOC SMI handler during ramstage finalize phase * * BIOS can't make CSME function disable as is due to POSTBOOT_SAI * restriction in place from CNP chipset. Hence create SMI Handler to * perform CSME function disabling logic during SMM mode. */ void smihandler_soc_at_finalize(void) { const struct soc_intel_cannonlake_config *config; const struct device *dev = dev_find_slot(0, PCH_DEVFN_CSE); if (!dev || !dev->chip_info) { printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", __func__); return ; } config = dev->chip_info; if (config->HeciEnabled == 0) pch_disable_heci(); } void smihandler_soc_check_illegal_access(uint32_t tco_sts) { if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM) && fast_spi_wpd_status())) return; /* * BWE is RW, so the SMI was caused by a * write to BWE, not by a write to the BIOS * * This is the place where we notice someone * is trying to tinker with the BIOS. We are * trying to be nice and just ignore it. A more * resolute answer would be to power down the * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); fast_spi_enable_wp(); } /* SMI handlers that should be serviced in SCI mode too. */ uint32_t smihandler_soc_get_sci_mask(void) { uint32_t sci_mask = SMI_HANDLER_SCI_EN(APM_STS_BIT) | SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT); return sci_mask; }