/**
* @brief Write to an I/O bus.
* @note The operation is not guaranteed to be atomic on all the
* architectures, for atomicity and/or portability reasons you may
* need to enclose port I/O operations between @p chSysLock() and
* @p chSysUnlock().
* @note The default implementation is non atomic and not necessarily
* optimal. Low level drivers may optimize the function by using
* specific hardware or coding.
*
* @param[in] bus the I/O bus, pointer to a @p IOBus structure
* @param[in] bits the bits to be written on the I/O bus. Values exceeding
* the bus width are masked so most significant bits are
* lost.
*
* @api
*/
void palWriteBus(IOBus *bus, ioportmask_t bits) {
chDbgCheck((bus != NULL) &&
(bus->bus_offset < PAL_IOPORTS_WIDTH), "palWriteBus");
palWriteGroup(bus->bus_portid, bus->bus_mask, bus->bus_offset, bits);
}
/* The PWM Counter Reset will put the PWM system in "ACTIVE" state, which
* is defined as the state when the channel is active and a compare event
* has not yet taken place.
*/
static void cdPwmCounterReset(PWMDriver *pwmp) {
(void) pwmp;
chSysLockFromIsr();
palWriteGroup (PWM_OUT_PORT, PWM_OUT_PORT_MASK, PWM_OUT_OFFSET, bldc.pwmOutT0);
// Calculate and initiate the state change
// Consider moving this to a thread to further slim down the ISR callback
if (!halIsCounterWithin(bldc.prevStateChange, bldc.nextStateChange)) {
// Prepare next state
if (bldc.directionFwd) {
bldc.nextState++;
}
else {
bldc.nextState--;
}
// Wrap the state counter
bldc.nextState = (bldc.nextState+bldc.stateCount)%bldc.stateCount;
// Prepare the next state change.
bldc.prevStateChange = bldc.nextStateChange;
bldc.nextStateChange += bldc.stateChangeInterval;
}
chSysUnlockFromIsr();
}
/* This function will start the PWM generator.
*/
extern void bldcInit(void) {
bldc.scheme = &pwmScheme;
bldc.state = 0; //Default to first state
bldc.nextState = 0;
bldc.directionFwd = TRUE;
bldc.stateChangeInterval = MS2RTT(20);
bldc.prevStateChange = halGetCounterValue();
bldc.nextStateChange = bldc.prevStateChange + bldc.stateChangeInterval;
bldc.pwmOutT0 = 0;
bldc.pwmOutT1 = 0;
bldc.stateCount = sizeof(pwmScheme)/3;
bldc.dutyCycle = 1800;
palWriteGroup (PWM_OUT_PORT, PWM_OUT_PORT_MASK, PWM_OUT_OFFSET, PWM_OFF);
palSetGroupMode (PWM_OUT_PORT, PWM_OUT_PORT_MASK, PWM_OUT_OFFSET, PAL_MODE_OUTPUT_PUSHPULL);
palSetPadMode (GPIOA, GPIOA_PIN1, PAL_MODE_INPUT_ANALOG);
pwmStart(&PWMD1, &pwmcfg);
// ADC trigger channel. This will trigger the ADC read at 95% of the cycle,
// when all the PWM outputs are set to 0
pwmEnableChannel (&PWMD1, PWM_ADCTRIG_CH, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, PWM_MAX_DUTY_CYCLE));
// Start the ADC
adcStart(&ADCD1, NULL);
}
/* The PWM Channel compare will put the PWM system in "IDLE" state, which
* is defined as the state when the channel is active and a compare event
* has taken place.
*/
static void cbPwmCh0Compare(PWMDriver *pwmp) {
(void) pwmp;
chSysLockFromIsr();
palWriteGroup (PWM_OUT_PORT, PWM_OUT_PORT_MASK, PWM_OUT_OFFSET, bldc.pwmOutT1);
// Do the state change before the next cycle.
// Consider moving this to a thread to further slim down the ISR callback
bldc.state = bldc.nextState;
bldc.pwmOutT0 = (*bldc.scheme)[bldc.state][0];
bldc.pwmOutT1 = (*bldc.scheme)[bldc.state][1];
chSysUnlockFromIsr();
}
extern void bldcKill(void) {
palWriteGroup (PWM_OUT_PORT, PWM_OUT_PORT_MASK, PWM_OUT_OFFSET, PWM_OFF);
pwmStop(&PWMD1);
}
