static void
print_460gx_sac(pciConfigPtr pcr)
{
CARD32 tmp;
/* Print generalities */
printf(" STATUS 0x%04x COMMAND 0x%04x\n",
pcr->pci_status, pcr->pci_command);
printf(" CLASS 0x%02x 0x%02x 0x%02x REVISION 0x%02x\n",
pcr->pci_base_class, pcr->pci_sub_class, pcr->pci_prog_if,
pcr->pci_rev_id);
tmp = pcr->pci_user_config;
pcr->pci_user_config = 0;
print_default_class(pcr);
pcr->pci_user_config = tmp;
/* Only print what XFree86 might be interested in */
if (pcr->busnum == 0) {
if ((pcr->devnum != 0x10) || (pcr->funcnum != 0))
return;
/* Get Chipset Bus Number */
cbn_460gx = (unsigned int)pciReadByte(pcr->tag, 0x0040);
printf(" CBN 0x%02x CBUSES 0x%02x\n",
cbn_460gx, pciReadByte(pcr->tag, 0x0044));
return;
}
if ((pcr->busnum != cbn_460gx) || (pcr->funcnum != 0))
return;
switch (pcr->devnum) {
case 0:
printf(" F16NUM 0x%02x F16CPL 0x%02x DEVNPRES 0x%08lx\n",
pciReadByte(pcr->tag, 0x0060), pciReadByte(pcr->tag, 0x0078),
(long)pciReadLong(pcr->tag, 0x0070));
return;
case 0x10:
printf(" TOM 0x%04x IORD 0x%04x\n",
pciReadWord(pcr->tag, 0x0050), pciReadWord(pcr->tag, 0x008E));
/* Fall through */
case 0x11: case 0x12: case 0x13:
case 0x14: case 0x15: case 0x16: case 0x17:
printf(" BUSNO 0x%02x SUBNO 0x%02x\n",
pciReadByte(pcr->tag, 0x0048), pciReadByte(pcr->tag, 0x0049));
printf(" VGASE 0x%02x PCIS 0x%02x IOR 0x%02x\n",
pciReadByte(pcr->tag, 0x0080), pciReadByte(pcr->tag, 0x0084),
pciReadByte(pcr->tag, 0x008C));
/* Fall through */
default:
return;
}
}
static void
print_460gx_pxb(pciConfigPtr pcr)
{
CARD32 tmp;
tmp = pcr->pci_user_config;
pcr->pci_user_config = 0;
print_header_type_0(pcr);
pcr->pci_user_config = tmp;
/* Only print what XFree86 might be interested in */
printf(" ERRCMD 0x%02x GAPEN 0x%02x\n",
pciReadByte(pcr->tag, 0x0046), pciReadByte(pcr->tag, 0x0060));
}
static int intel_8xx_fetch_size(void)
{
u8_t temp;
temp = pciReadByte(bridge->PciTag, INTEL_APSIZE);
return __intel_8xx_fetch_size(temp);
}
static void
print_460gx_gxb(pciConfigPtr pcr)
{
CARD32 tmp;
tmp = pcr->pci_user_config;
pcr->pci_user_config = 0;
print_header_type_0(pcr);
pcr->pci_user_config = tmp;
/* Only print what XFree86 might be interested in */
printf(" BAPBASE 0x%08lx%08lx AGPSIZ 0x%02x VGAGE 0x%02x\n",
(long)pciReadLong(pcr->tag, 0x009C),
(long)pciReadLong(pcr->tag, 0x0098),
pciReadByte(pcr->tag, 0x00A2), pciReadByte(pcr->tag, 0x0060));
}
static void
print_460gx_sac(pciConfigPtr pcr)
{
CARD32 tmp;
tmp = pcr->pci_user_config;
pcr->pci_user_config = 0;
print_header_type_0(pcr);
pcr->pci_user_config = tmp;
/* Only print what XFree86 might be interested in */
if (pcr->busnum == 0) {
if ((pcr->devnum != 0x10) || (pcr->funcnum != 0))
return;
/* Get Chipset Bus Number */
cbn_460gx = (unsigned int)pciReadByte(pcr->tag, 0x0040);
printf(" CBN 0x%02x CBUSES 0x%02x\n",
cbn_460gx, pciReadByte(pcr->tag, 0x0044));
return;
}
if ((pcr->busnum != cbn_460gx) || (pcr->funcnum != 0))
return;
switch (pcr->devnum) {
case 0:
printf(" F16NUM 0x%02x F16CPL 0x%02x DEVNPRES 0x%08lx\n",
pciReadByte(pcr->tag, 0x0060), pciReadByte(pcr->tag, 0x0078),
(long)pciReadLong(pcr->tag, 0x0070));
return;
case 0x10:
printf(" TOM 0x%04x IORD 0x%04x\n",
pciReadWord(pcr->tag, 0x0050), pciReadWord(pcr->tag, 0x008E));
/* Fall through */
case 0x11: case 0x12: case 0x13:
case 0x14: case 0x15: case 0x16: case 0x17:
printf(" BUSNO 0x%02x SUBNO 0x%02x\n",
pciReadByte(pcr->tag, 0x0048), pciReadByte(pcr->tag, 0x0049));
printf(" VGASE 0x%02x PCIS 0x%02x IOR 0x%02x\n",
pciReadByte(pcr->tag, 0x0080), pciReadByte(pcr->tag, 0x0084),
pciReadByte(pcr->tag, 0x008C));
/* Fall through */
default:
return;
}
}
/*
* This function is called to emulate the various settings in a P2P or CardBus
* bridge's control register using one of a 460GX's SAC host bridges.
*/
static CARD16
Control460GXBridge(int bus, CARD16 mask, CARD16 value)
{
pciConfigPtr pPCI;
PCITAG tag;
CARD16 current = 0;
CARD8 tmp;
if ((pPCI = Verify460GXBus(bus))) {
/* Start with VGA enablement */
tmp = pciReadByte(pPCI->tag, VGASE);
if (tmp & 0x01) {
current |= PCI_PCI_BRIDGE_VGA_EN;
if ((mask & PCI_PCI_BRIDGE_VGA_EN) &&
!(value & PCI_PCI_BRIDGE_VGA_EN))
pciWriteByte(pPCI->tag, VGASE, tmp & ~0x01);
} else {
if (mask & value & PCI_PCI_BRIDGE_VGA_EN)
pciWriteByte(pPCI->tag, VGASE, tmp | 0x01);
}
/* Move on to master abort failure enablement */
if (has_err_460gx[pPCI->devnum - 0x10]) {
tag = PCI_MAKE_TAG(pPCI->busnum, pPCI->devnum, pPCI->funcnum + 1);
tmp = pciReadByte(tag, ERRCMD);
if (tmp & 0x01) {
current |= PCI_PCI_BRIDGE_MASTER_ABORT_EN;
if ((mask & PCI_PCI_BRIDGE_MASTER_ABORT_EN) &&
!(value & PCI_PCI_BRIDGE_MASTER_ABORT_EN))
pciWriteByte(tag, ERRCMD, tmp & ~0x01);
} else {
if (mask & value & PCI_PCI_BRIDGE_MASTER_ABORT_EN)
pciWriteByte(tag, ERRCMD, tmp | 0x01);
}
}
/* Put emulation of any other P2P bridge control here */
}
return (current & ~mask) | (value & mask);
}
static void
print_460gx_pxb(pciConfigPtr pcr)
{
CARD32 tmp;
/* Print generalities */
printf(" STATUS 0x%04x COMMAND 0x%04x\n",
pcr->pci_status, pcr->pci_command);
printf(" CLASS 0x%02x 0x%02x 0x%02x REVISION 0x%02x\n",
pcr->pci_base_class, pcr->pci_sub_class, pcr->pci_prog_if,
pcr->pci_rev_id);
tmp = pcr->pci_user_config;
pcr->pci_user_config = 0;
print_default_class(pcr);
pcr->pci_user_config = tmp;
/* Only print what XFree86 might be interested in */
printf(" ERRCMD 0x%02x GAPEN 0x%02x\n",
pciReadByte(pcr->tag, 0x0046), pciReadByte(pcr->tag, 0x0060));
}
static void
print_460gx_gxb(pciConfigPtr pcr)
{
CARD32 tmp;
/* Print generalities */
printf(" STATUS 0x%04x COMMAND 0x%04x\n",
pcr->pci_status, pcr->pci_command);
printf(" CLASS 0x%02x 0x%02x 0x%02x REVISION 0x%02x\n",
pcr->pci_base_class, pcr->pci_sub_class, pcr->pci_prog_if,
pcr->pci_rev_id);
tmp = pcr->pci_user_config;
pcr->pci_user_config = 0;
print_default_class(pcr);
pcr->pci_user_config = tmp;
/* Only print what XFree86 might be interested in */
printf(" BAPBASE 0x%08lx%08lx AGPSIZ 0x%02x VGAGE 0x%02x\n",
(long)pciReadLong(pcr->tag, 0x009C),
(long)pciReadLong(pcr->tag, 0x0098),
pciReadByte(pcr->tag, 0x00A2), pciReadByte(pcr->tag, 0x0060));
}
static void
print_simba(pciConfigPtr pcr)
{
int i;
CARD8 io, mem;
print_header_type_1(pcr);
printf(" TICK 0x%08lx SECCNTL 0x%02x\n", (long)
pciReadLong(pcr->tag, 0x00b0), pciReadByte(pcr->tag, 0x00dd));
printf(" MASTER RETRIES: PRIMARY 0x%02x, SECONDARY 0x%02x\n",
pciReadByte(pcr->tag, 0x00c0), pciReadByte(pcr->tag, 0x00dc));
printf(" TARGET RETRIES: PIO 0x%02x, DMA 0x%02x\n",
pciReadByte(pcr->tag, 0x00d8), pciReadByte(pcr->tag, 0x00da));
printf(" TARGET LATENCY: PIO 0x%02x, DMA 0x%02x\n",
pciReadByte(pcr->tag, 0x00d9), pciReadByte(pcr->tag, 0x00db));
printf(" DMA AFSR 0x%08lx%08lx AFAR 0x%08lx%08lx\n",
(long)pciReadLong(pcr->tag, 0x00cc),
(long)pciReadLong(pcr->tag, 0x00c8),
(long)pciReadLong(pcr->tag, 0x00d4),
(long)pciReadLong(pcr->tag, 0x00d0));
printf(" PIO AFSR 0x%08lx%08lx AFAR 0x%08lx%08lx\n",
(long)pciReadLong(pcr->tag, 0x00ec),
(long)pciReadLong(pcr->tag, 0x00e8),
(long)pciReadLong(pcr->tag, 0x00f4),
(long)pciReadLong(pcr->tag, 0x00f0));
printf(" PCI CNTL 0x%08lx%08lx DIAG 0x%08lx%08lx\n",
(long)pciReadLong(pcr->tag, 0x00e4),
(long)pciReadLong(pcr->tag, 0x00e0),
(long)pciReadLong(pcr->tag, 0x00fc),
(long)pciReadLong(pcr->tag, 0x00f8));
printf(" MAPS: I/O 0x%02x, MEM 0x%02x\n",
(io = pciReadByte(pcr->tag, 0x00de)),
(mem = pciReadByte(pcr->tag, 0x00df)));
for (i = 0; i < 8; i++)
if (io & (1 << i))
printf(" BUS I/O 0x%06x-0x%06x\n", i << 21, ((i + 1) << 21) - 1);
for (i = 0; i < 8; i++)
if (mem & (1 << i))
printf(" BUS MEM 0x%08x-0x%08x\n", i << 29, ((i + 1) << 29) - 1);
}
static int intel_845_configure()
{
u32_t temp;
u8_t temp2;
aper_size_t *current_size;
current_size = bridge->current_size;
/* aperture size */
pciWriteByte(bridge->PciTag, INTEL_APSIZE, current_size->size_value);
dbgprintf("INTEL_APSIZE %d\n", current_size->size_value );
if (bridge->apbase_config != 0)
{
pciWriteLong(bridge->PciTag, AGP_APBASE, bridge->apbase_config);
}
else
{
/* address to map to */
temp = pciReadLong(bridge->PciTag, AGP_APBASE);
bridge->gart_addr = (temp & PCI_MAP_MEMORY_ADDRESS_MASK);
bridge->apbase_config = temp;
}
dbgprintf("AGP_APBASE %x\n", temp );
/* attbase - aperture base */
pciWriteLong(bridge->PciTag, INTEL_ATTBASE, bridge->gatt_dma);
/* agpctrl */
pciWriteLong(bridge->PciTag, INTEL_AGPCTRL, 0x0000);
/* agpm */
temp2 = pciReadByte(bridge->PciTag, INTEL_I845_AGPM);
pciWriteByte(bridge->PciTag, INTEL_I845_AGPM, temp2 | (1 << 1));
/* clear any possible error conditions */
pciWriteWord(bridge->PciTag, INTEL_I845_ERRSTS, 0x001c);
return 0;
}
/*
* This checks for, and validates, the presence of the 460GX chipset, and sets
* cbn_460gx to a positive value accordingly. This function returns TRUE if
* the chipset scan is to be stopped, or FALSE if the scan is to move on to the
* next chipset.
*/
Bool
xf86PreScan460GX(void)
{
pciBusInfo_t *pBusInfo;
PCITAG tag;
CARD32 tmp;
int i, devno;
/* Bus zero should already be set up */
if (!(pBusInfo = pciBusInfo[0])) {
cbn_460gx = -1;
return FALSE;
}
/* First look for a 460GX's primary host bridge */
tag = PCI_MAKE_TAG(0, 0x10, 0);
if (pciReadLong(tag, PCI_ID_REG) != DEVID(INTEL, 460GX_SAC)) {
cbn_460gx = -1;
return FALSE;
}
/* Get CBN (Chipset bus number) */
if (!(cbn_460gx = (unsigned int)pciReadByte(tag, CBN))) {
/* Sanity check failed */
cbn_460gx = -1;
return TRUE;
}
if (pciNumBuses <= cbn_460gx)
pciNumBuses = cbn_460gx + 1;
/* Set up bus CBN */
if (!pciBusInfo[cbn_460gx]) {
pciBusInfo[cbn_460gx] = xnfalloc(sizeof(pciBusInfo_t));
*pciBusInfo[cbn_460gx] = *pBusInfo;
}
tag = PCI_MAKE_TAG(cbn_460gx, 0, 0);
if (pciReadLong(tag, PCI_ID_REG) != DEVID(INTEL, 460GX_SAC)) {
/* Sanity check failed */
cbn_460gx = -1;
return TRUE;
}
/*
* Find out which CBN devices the firmware thinks are present. Of these,
* we are only interested in devices 0x10 through 0x17.
*/
cbdevs_460gx = pciReadLong(tag, DEVNPRES);
for (i = 0, devno = 0x10; devno <= 0x17; i++, devno++) {
tag = PCI_MAKE_TAG(cbn_460gx, devno, 0);
if (pciReadLong(tag, PCI_ID_REG) != DEVID(INTEL, 460GX_SAC)) {
/* Sanity check failed */
cbn_460gx = -1;
return TRUE;
}
if (devno == 0x10)
iord_460gx = pciReadWord(tag, IORD);
busno_460gx[i] = (unsigned int)pciReadByte(tag, BUSNO);
subno_460gx[i] = (unsigned int)pciReadByte(tag, SUBNO);
pcis_460gx[i] = pciReadByte(tag, PCIS);
ior_460gx[i] = pciReadByte(tag, IOR);
has_err_460gx[i] = err_460gx[i] = 0; /* Insurance */
tag = PCI_MAKE_TAG(cbn_460gx, devno, 1);
tmp = pciReadLong(tag, PCI_ID_REG);
switch (tmp) {
case DEVID(INTEL, 460GX_PXB):
case DEVID(INTEL, 460GX_WXB):
if (cbdevs_460gx & (1 << devno)) {
/* Sanity check failed */
cbn_460gx = -1;
return TRUE;
}
/*
* XXX I don't have WXB docs, but PCI register dumps indicate that
* the registers we are interested in are consistent with those of
* the PXB.
*/
err_460gx[i] = pciReadByte(tag, ERRCMD);
has_err_460gx[i] = 1;
break;
case DEVID(INTEL, 460GX_GXB_1):
if (cbdevs_460gx & (1 << devno)) {
/* Sanity check failed */
cbn_460gx = -1;
return TRUE;
}
/*
* XXX GXB isn't documented to have an ERRCMD register, nor any
* other means of failing master aborts. For now, assume master
* aborts are always allowed to complete normally.
*/
break;
default:
if (((CARD16)(tmp + 1U) <= (CARD16)1U) &&
(cbdevs_460gx & (1U << devno)))
break;
/* Sanity check failed */
cbn_460gx = -1;
return TRUE;
}
}
/* Allow master aborts to complete normally */
for (i = 0, devno = 0x10; devno <= 0x17; i++, devno++) {
if (!(err_460gx[i] & 0x01))
continue;
pciWriteByte(PCI_MAKE_TAG(cbn_460gx, devno, 1),
ERRCMD, err_460gx[i] & ~0x01);
}
/*
* The 460GX spec says that any access to busses higher than CBN will be
* master-aborted. It seems possible however that this is not the case in
* all 460GX implementations. For now, limit the bus scan to CBN, unless
* we have already found a higher bus number.
*/
for (i = 0; subno_460gx[i] < cbn_460gx; ) {
if (++i < 8)
continue;
pciMaxBusNum = cbn_460gx + 1;
break;
}
return TRUE;
}
static void
print_simba(pciConfigPtr pcr)
{
int i;
CARD8 io, mem;
printf(" STATUS 0x%04x COMMAND 0x%04x\n",
pcr->pci_status, pcr->pci_command);
printf(" CLASS 0x%02x 0x%02x 0x%02x REVISION 0x%02x\n",
pcr->pci_base_class, pcr->pci_sub_class, pcr->pci_prog_if,
pcr->pci_rev_id);
printf(" HEADER 0x%02x LATENCY 0x%02x CACHE 0x%02x\n",
pcr->pci_header_type, pcr->pci_latency_timer,
pcr->pci_cache_line_size);
printf(" PRIBUS 0x%02x SECBUS 0x%02x SUBBUS 0x%02x SECLT 0x%02x\n",
pcr->pci_primary_bus_number, pcr->pci_secondary_bus_number,
pcr->pci_subordinate_bus_number, pcr->pci_secondary_latency_timer);
printf(" SECSTATUS 0x%04x\n",
pcr->pci_secondary_status);
printf(" %sFAST_B2B %sSEC_BUS_RST %sM_ABRT %sVGA_EN %sISA_EN"
" %sSERR_EN %sPERR_EN\n",
(pcr->pci_bridge_control & PCI_B_FAST_B_B) ? "" : "NO_",
(pcr->pci_bridge_control & PCI_B_SB_RESET) ? "" : "NO_",
(pcr->pci_bridge_control & PCI_B_M_ABORT) ? "" : "NO_",
(pcr->pci_bridge_control & PCI_B_VGA_EN) ? "" : "NO_",
(pcr->pci_bridge_control & PCI_B_ISA_EN) ? "" : "NO_",
(pcr->pci_bridge_control & PCI_B_SERR_EN) ? "" : "NO_",
(pcr->pci_bridge_control & PCI_B_P_ERR) ? "" : "NO_");
printf(" TICK 0x%08lx SECCNTL 0x%02x\n", (long)
pciReadLong(pcr->tag, 0x00b0), pciReadByte(pcr->tag, 0x00dd));
printf(" MASTER RETRIES: PRIMARY 0x%02x, SECONDARY 0x%02x\n",
pciReadByte(pcr->tag, 0x00c0), pciReadByte(pcr->tag, 0x00dc));
printf(" TARGET RETRIES: PIO 0x%02x, DMA 0x%02x\n",
pciReadByte(pcr->tag, 0x00d8), pciReadByte(pcr->tag, 0x00da));
printf(" TARGET LATENCY: PIO 0x%02x, DMA 0x%02x\n",
pciReadByte(pcr->tag, 0x00d9), pciReadByte(pcr->tag, 0x00db));
printf(" DMA AFSR 0x%08lx%08lx AFAR 0x%08lx%08lx\n",
(long)pciReadLong(pcr->tag, 0x00cc),
(long)pciReadLong(pcr->tag, 0x00c8),
(long)pciReadLong(pcr->tag, 0x00d4),
(long)pciReadLong(pcr->tag, 0x00d0));
printf(" PIO AFSR 0x%08lx%08lx AFAR 0x%08lx%08lx\n",
(long)pciReadLong(pcr->tag, 0x00ec),
(long)pciReadLong(pcr->tag, 0x00e8),
(long)pciReadLong(pcr->tag, 0x00f4),
(long)pciReadLong(pcr->tag, 0x00f0));
printf(" PCI CNTL 0x%08lx%08lx DIAG 0x%08lx%08lx\n",
(long)pciReadLong(pcr->tag, 0x00e4),
(long)pciReadLong(pcr->tag, 0x00e0),
(long)pciReadLong(pcr->tag, 0x00fc),
(long)pciReadLong(pcr->tag, 0x00f8));
printf(" MAPS: I/O 0x%02x, MEM 0x%02x\n",
(io = pciReadByte(pcr->tag, 0x00de)),
(mem = pciReadByte(pcr->tag, 0x00df)));
for (i = 0; i < 8; i++)
if (io & (1 << i))
printf(" BUS I/O 0x%06x-0x%06x\n", i << 21, ((i + 1) << 21) - 1);
for (i = 0; i < 8; i++)
if (mem & (1 << i))
printf(" BUS MEM 0x%08x-0x%08x\n", i << 29, ((i + 1) << 29) - 1);
}
