static bool init_vx86(void) {
int i;
for (i=0; i<(int)(sizeof(VX86_pciDev)/sizeof(VX86_pciDev[0])); i++) VX86_pciDev[i] = NULL;
// get North Bridge fun0 & South Bridge fun0 & IDE PCI-CFG
if ((VX86_pciDev[VX86_NB] = pci_Alloc(0x00, 0x00, 0x00)) == NULL) goto FAIL_INITVX86;
if ((VX86_pciDev[VX86_SB] = pci_Alloc(0x00, 0x07, 0x00)) == NULL) goto FAIL_INITVX86;
if ((VX86_pciDev[VX86_IDE] = pci_Alloc(0x00, 0x0c, 0x00)) == NULL) goto FAIL_INITVX86;
// now we are allowed to call get_cpuid()
if ((VX86_cpuID = get_cpuid()) == CPU_UNSUPPORTED) goto FAIL_INITVX86;
if (vx86_CpuID() != CPU_VORTEX86SX)
{
// North Bridge fun1 exists (note NB fun1 isn't a normal PCI device -- its vid & did are 0xffff)
if ((VX86_pciDev[VX86_NB1] = pci_Alloc(0x00, 0x00, 0x01)) == NULL) goto FAIL_INITVX86;
}
if (vx86_CpuID() == CPU_VORTEX86EX || vx86_CpuID() == CPU_VORTEX86DX2 || vx86_CpuID() == CPU_VORTEX86DX3)
{
// South Bridge fun1 exists (note SB fun1 isn't a normal PCI device -- its vid & did are 0xffff)
if ((VX86_pciDev[VX86_SB1] = pci_Alloc(0x00, 0x07, 0x01)) == NULL) goto FAIL_INITVX86;
}
return true;
FAIL_INITVX86:
for (i=0; i<(int)(sizeof(VX86_pciDev)/sizeof(VX86_pciDev[0])); i++)
{
pci_Free(VX86_pciDev[i]);
VX86_pciDev[i] = NULL;
}
err_print((char*)"%s: fail to setup system PCI devices!\n", __FUNCTION__);
return false;
}
DMPAPI(void*) pci_Find(unsigned short vid, unsigned short did) {
unsigned long pciid = ((unsigned long)did << 16) + (unsigned long)vid;
unsigned long tmpid, pciaddr;
unsigned char tmpht;
int bus, dev, fun;
if (pciid == 0xffffffffUL) return NULL;
for (bus=0; bus<256; bus++)
for (dev=0; dev<32; dev++)
for (fun=0; fun<8; fun++)
{
pciaddr = PCI_GET_CF8(bus, dev, fun);
io_DisableINT();
tmpid = pci_indw(pciaddr);
io_RestoreINT();
if (tmpid == pciid) return pci_Alloc((unsigned char)bus, (unsigned char)dev, (unsigned char)fun);
if (fun == 0)
{
if (tmpid == 0xffffffffUL) break; // invalid PCI device (note: shouldn't do this optimization for Vortex86DX2's internal PCI devices)
io_DisableINT();
tmpht = pci_inb(pciaddr + 0x0eL);
io_RestoreINT();
if ((tmpht & 0x80) == 0) break; // single-function PCI device
}
} // end for (fun=...
return NULL;
}
DMPAPI(void*) pci_Find(unsigned short vid, unsigned short did) { // don't use this function in the init of io system
unsigned long pciid = ((unsigned long)did << 16) + (unsigned long)vid;
unsigned long tmpid, pciaddr;
int bus, dev, fun;
if (pciid == 0xffffffffUL) return NULL;
for (bus=0; bus<256; bus++)
for (dev=0; dev<32; dev++)
for (fun=0; fun<8; fun++)
{
pciaddr = PCI_GET_CF8(bus, dev, fun);
tmpid = pci_indw(pciaddr);
if (tmpid == pciid) return pci_Alloc((unsigned char)bus, (unsigned char)dev, (unsigned char)fun);
if (fun == 0)
{
if (tmpid == 0xffffffffUL) // invalid PCI device
{
// NOTE: shouldn't do this optimization for Vortex86DX2/DX3/EX's internal PCI devices (where fun0 may be shutdown but fun1 is still enabled)
if ((vx86_CpuID() == CPU_VORTEX86DX2) || (vx86_CpuID() == CPU_VORTEX86DX3) || (vx86_CpuID() == CPU_VORTEX86EX)) { /* do nothing ... */ } else break;
}
if ((pci_inb(pciaddr + 0x0eL) & 0x80) == 0) break; // single-function PCI device
}
} // end for (fun=...
return NULL;
}
void SPIClass::begin()
{
if (!initialized) {
void *pciDev = NULL;
// Get SPI device base address
pciDev = pci_Alloc(0x00, 0x10, 0x01); // PCI SPI configuration space
if(pciDev == NULL) {printf("SPI device don't exist\n"); return;}
SPI_IOaddr = (unsigned)(pci_In16(pciDev, 0x10) & 0xFFFFFFF0L); // get SPI base address
#if defined DEBUG_MODE
printf("SPI base address = %04X\n", SPI_IOaddr);
#endif
pci_Free(pciDev);
WriteCTRR(FULLDUPEX + SPI_MODE0 + RESET);
io_outpb(SPI_IOaddr + 7, FULLDUPEX); // full-dupex
io_outpb(SPI_IOaddr + 7, io_inpb(SPI_IOaddr + 7) & 0xF1 | SPI_MODE0); // set mode
io_outpb(SPI_IOaddr + 0x0b, 0x08); // delay clk between two transfers
//SOURCE clock/(2 * SPI_CLOCK_DIV)
setClockDivider(13); // 100/(2*13) ~= 4MHz
useFIFO();
detachInterrupt();
io_outpb(SPI_IOaddr + 4, 0x01); // set CS = high
// Set SS to high so a connected chip will be "deselected" by default
pinMode(SS, OUTPUT);
digitalWrite(SS, HIGH);
}
initialized++; // reference count
}
static void write_cmos(unsigned char address, unsigned char buf)
{
if(address >= EEPROMSIZE_BANK0) // 0~199
return ;
#if (defined(DMP_DOS_BC) || defined(DMP_DOS_DJGPP) || defined(DMP_DOS_WATCOM))
io_DisableINT();
#elif defined (DMP_LINUX)
lockCMOS();
#endif
void *pciDev = NULL;
pciDev = pci_Alloc(0x00, 0x07, 0x00);
if(pciDev == NULL)
{
#if (defined(DMP_DOS_BC) || defined(DMP_DOS_DJGPP) || defined(DMP_DOS_WATCOM))
Serial.print("CMOS device doesn't exist\n");
#elif (defined(DMP_LINUX))
printf("CMOS device doesn't exist\n");
#endif
return;
}
unsigned long int reg;
reg = pci_In32(pciDev, 0xc0);
if(address == 20 || address == 22) //special case
{
//Set bit 3 to access high 128 bytes RTC SRAM
pci_Out32(pciDev, 0xc0, reg | 0x00000008);
address = (address == 20)? 26:27;
io_outpb(0x70, address);
}
else if(address < 100) // 0~99 low page
{
//clear bit 3 to access low 128 bytes RTC SRAM
pci_Out32(pciDev, 0xc0, reg & 0xfffffff7);
io_outpb(0x70, address + 28);
}
else// 100~199 high page
{
//Set bit 3 to access high 128 bytes RTC SRAM
pci_Out32(pciDev, 0xc0, reg | 0x00000008);
address -= 100;
io_outpb(0x70, address + 28);
}
io_outpb(0x71, buf);
// Restore old register value
pci_Out32(pciDev, 0xc0, reg);
pci_Free(pciDev);
#if (defined(DMP_DOS_BC) || defined(DMP_DOS_DJGPP) || defined(DMP_DOS_WATCOM))
io_RestoreINT();
#elif defined (DMP_LINUX)
unLockCMOS();
#endif
}
void WIFI_SPIClass::begin() {
void *pciDev = NULL;
if(io_Init() == false)
return;
// Get SPI device base address
pciDev = pci_Alloc(0x00, 0x10, 0x01); // PCI SPI configuration space
if(pciDev == NULL) {printf("WiFi-SPI device don't exist\n"); return;}
WIFI_SPI_IOaddr = (unsigned)(pci_In16(pciDev, 0x10) & 0xFFFFFFF0L); // get SPI base address
#if defined WIFI_DEBUG_MODE
printf("WiFi-SPI base address = %04X\n", WIFI_SPI_IOaddr);
#endif
pci_Free(pciDev);
WIFI_WriteCTRR(WIFI_FULLDUPEX + WIFI_SPI_MODE0 + WIFI_RESET);
io_outpb(WIFI_SPI_IOaddr + 7, WIFI_FULLDUPEX); // full-dupex
io_outpb(WIFI_SPI_IOaddr + 7, io_inpb(WIFI_SPI_IOaddr + 7) & 0xF1 | WIFI_SPI_MODE0); // set mode
io_outpb(WIFI_SPI_IOaddr + 0x0b, 0x08); // delay clk between two transfers
//SOURCE clock/(2 * SPI_CLOCK_DIV)
setClockDivider(WIFI_SPI_CLOCK_DIV800); // 125k Hz
WIFI_useFIFO();
detachInterrupt();
io_outpb(WIFI_SPI_IOaddr + 4, 0x01); // set CS = high
// Set SS to high so a connected chip will be "deselected" by default
digitalWrite(SS, HIGH);
// When the SS pin is set as OUTPUT, it can be used as
// a general purpose output port (it doesn't influence
// SPI operations).
//pinMode(SS, OUTPUT);
// Warning: if the SS pin ever becomes a LOW INPUT then SPI
// automatically switches to Slave, so the data direction of
// the SS pin MUST be kept as OUTPUT.
//SPCR |= _BV(MSTR);
//SPCR |= _BV(SPE);
// Set direction register for SCK and MOSI pin.
// MISO pin automatically overrides to INPUT.
// By doing this AFTER enabling SPI, we avoid accidentally
// clocking in a single bit since the lines go directly
// from "input" to SPI control.
// http://code.google.com/p/arduino/issues/detail?id=888
//pinMode(SCK, OUTPUT);
//pinMode(MOSI, OUTPUT);
}
