ACPI_STATUS
AcpiOsReadPciConfiguration (
ACPI_PCI_ID *PciId,
UINT32 Register,
void *Value,
UINT32 Width)
{
u_int32_t byte_width = Width / 8;
u_int32_t val;
if (!pci_cfgregopen())
return(AE_NOT_EXIST);
val = pci_cfgregread(PciId->Bus, PciId->Device, PciId->Function, Register, byte_width);
switch (Width) {
case 8:
*(u_int8_t *)Value = val & 0xff;
break;
case 16:
*(u_int16_t *)Value = val & 0xffff;
break;
case 32:
*(u_int32_t *)Value = val;
break;
default:
/* debug trap goes here */
break;
}
return(AE_OK);
}
static uint32_t
qpi_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
u_int reg, int bytes)
{
return (pci_cfgregread(bus, slot, func, reg, bytes));
}
/*
* Initialise access to PCI configuration space
*/
int
pci_cfgregopen(void)
{
static int once = 0;
uint64_t pciebar;
uint16_t did, vid;
if (!once) {
mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
once = 1;
}
if (cfgmech != CFGMECH_NONE)
return (1);
cfgmech = CFGMECH_1;
/*
* Grope around in the PCI config space to see if this is a
* chipset that is capable of doing memory-mapped config cycles.
* This also implies that it can do PCIe extended config cycles.
*/
/* Check for supported chipsets */
vid = pci_cfgregread(0, 0, 0, PCIR_VENDOR, 2);
did = pci_cfgregread(0, 0, 0, PCIR_DEVICE, 2);
switch (vid) {
case 0x8086:
switch (did) {
case 0x3590:
case 0x3592:
/* Intel 7520 or 7320 */
pciebar = pci_cfgregread(0, 0, 0, 0xce, 2) << 16;
pcie_cfgregopen(pciebar, 0, 255);
break;
case 0x2580:
case 0x2584:
case 0x2590:
/* Intel 915, 925, or 915GM */
pciebar = pci_cfgregread(0, 0, 0, 0x48, 4);
pcie_cfgregopen(pciebar, 0, 255);
break;
}
}
return (1);
}
/* XXX: Note that this is identical to pci_pir_search_irq(). */
static uint8_t
acpi_pci_link_search_irq(int bus, int device, int pin)
{
uint32_t value;
uint8_t func, maxfunc;
/* See if we have a valid device at function 0. */
value = pci_cfgregread(bus, device, 0, PCIR_HDRTYPE, 1);
if ((value & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
return (PCI_INVALID_IRQ);
if (value & PCIM_MFDEV)
maxfunc = PCI_FUNCMAX;
else
maxfunc = 0;
/* Scan all possible functions at this device. */
for (func = 0; func <= maxfunc; func++) {
value = pci_cfgregread(bus, device, func, PCIR_DEVVENDOR, 4);
if (value == 0xffffffff)
continue;
value = pci_cfgregread(bus, device, func, PCIR_INTPIN, 1);
/*
* See if it uses the pin in question. Note that the passed
* in pin uses 0 for A, .. 3 for D whereas the intpin
* register uses 0 for no interrupt, 1 for A, .. 4 for D.
*/
if (value != pin + 1)
continue;
value = pci_cfgregread(bus, device, func, PCIR_INTLINE, 1);
if (bootverbose)
printf(
"ACPI: Found matching pin for %d.%d.INT%c at func %d: %d\n",
bus, device, pin + 'A', func, value);
if (value != PCI_INVALID_IRQ)
return (value);
}
return (PCI_INVALID_IRQ);
}
ACPI_STATUS
AcpiOsReadPciConfiguration(ACPI_PCI_ID *PciId, UINT32 Register, UINT64 *Value,
UINT32 Width)
{
int bytes = Width / 8;
if (Width == 64)
return (AE_SUPPORT);
if (!pci_cfgregopen())
return (AE_NOT_EXIST);
*Value = pci_cfgregread(PciId->Bus, PciId->Device,
PciId->Function, Register, bytes);
*Value &= (1 << (bytes * 8)) - 1;
return (AE_OK);
}
ACPI_STATUS
AcpiOsReadPciConfiguration(ACPI_PCI_ID *PciId, UINT32 Register, UINT64 *Value,
UINT32 Width)
{
#ifdef __aarch64__
/* ARM64TODO: Add pci support */
return (AE_SUPPORT);
#else
if (Width == 64)
return (AE_SUPPORT);
if (!pci_cfgregopen())
return (AE_NOT_EXIST);
*(UINT64 *)Value = pci_cfgregread(PciId->Bus, PciId->Device,
PciId->Function, Register, Width / 8);
return (AE_OK);
#endif
}
/*
* Look for a PCI bus with the specified bus address. If one is found,
* add a pcib device and return 0. Otherwise, return an error code.
*/
static int
qpi_probe_pcib(device_t dev, int bus)
{
struct qpi_device *qdev;
device_t child;
uint32_t devid;
/*
* If a PCI bus already exists for this bus number, then
* fail.
*/
if (pci_find_bsf(bus, 0, 0) != NULL)
return (EEXIST);
/*
* Attempt to read the device id for device 0, function 0 on
* the bus. A value of 0xffffffff means that the bus is not
* present.
*/
devid = pci_cfgregread(bus, 0, 0, PCIR_DEVVENDOR, 4);
if (devid == 0xffffffff)
return (ENOENT);
if ((devid & 0xffff) != 0x8086) {
device_printf(dev,
"Device at pci%d.0.0 has non-Intel vendor 0x%x\n", bus,
devid & 0xffff);
return (ENXIO);
}
child = BUS_ADD_CHILD(dev, 0, "pcib", -1);
if (child == NULL)
panic("%s: failed to add pci bus %d", device_get_nameunit(dev),
bus);
qdev = bsd_malloc(sizeof(struct qpi_device), M_QPI, M_WAITOK);
qdev->qd_pcibus = bus;
device_set_ivars(child, qdev);
return (0);
}
u_int32_t
legacy_pcib_read_config(device_t dev, int bus, int slot, int func,
int reg, int bytes)
{
return(pci_cfgregread(bus, slot, func, reg, bytes));
}
HPT_U32 pcicfg_read_dword(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg)
{
return (HPT_U32)pci_cfgregread(bus, dev, func, reg, 4);;
}/* PCI space access */
HPT_U32 pcicfg_read_dword(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg)
{
return (HPT_U32)pci_cfgregread(bus, dev, func, reg, 4);
}
/* PCI space access */
HPT_U8 pcicfg_read_byte (HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg)
{
return (HPT_U8)pci_cfgregread(bus, dev, func, reg, 1);
}
