static uint64_t ppc_pci_io_read(void *opaque, hwaddr addr,
unsigned int size)
{
PREPPCIState *s = opaque;
PCIHostState *phb = PCI_HOST_BRIDGE(s);
return pci_data_read(phb->bus, PPC_PCIIO_config(addr), size);
}
static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr)
{
PREPPCIState *s = opaque;
uint32_t val;
val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 1);
return val;
}
static uint64_t pci_vpb_config_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
uint32_t val;
val = pci_data_read(opaque, vpb_pci_config_addr(addr), size);
return val;
}
static uint64_t pci_host_data_read(void *opaque,
hwaddr addr, unsigned len)
{
PCIHostState *s = opaque;
uint32_t val;
val = pci_data_read(s->bus, s->config_reg | (addr & 3), len);
return val;
}
static uint32_t pci_vpb_config_readl (void *opaque, target_phys_addr_t addr)
{
uint32_t val;
val = pci_data_read(opaque, vpb_pci_config_addr (addr), 4);
#ifdef TARGET_WORDS_BIGENDIAN
val = bswap32(val);
#endif
return val;
}
static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
{
PREPPCIState *s = opaque;
uint32_t val;
val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 4);
#ifdef TARGET_WORDS_BIGENDIAN
val = bswap32(val);
#endif
return val;
}
static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr)
{
SHPCIC *pcic = p;
switch(addr) {
case 0 ... 0xfc:
return le32_to_cpup((uint32_t*)(pcic->dev->config + addr));
case 0x1c0:
return pcic->par;
case 0x220:
return pci_data_read(pcic->bus, pcic->par, 4);
}
return 0;
}
static uint32_t pci_vpb_config_readb (void *opaque, target_phys_addr_t addr)
{
uint32_t val;
val = pci_data_read(opaque, vpb_pci_config_addr (addr), 1);
return val;
}
/* PCI config space reads/writes, to byte-word addressable memory. */
static uint64_t bw_conf1_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
PCIBus *b = opaque;
return pci_data_read(b, addr, size);
}
static uint64_t dino_config_data_read(void *opaque, hwaddr addr, unsigned len)
{
PCIHostState *s = opaque;
return pci_data_read(s->bus, s->config_reg | (addr & 3), len);
}
static uint32_t sh_pci_mem_read (SHPCIC *pcic, target_phys_addr_t addr,
int size)
{
return pci_data_read(pcic->bus, addr + pcic->mbr, size);
}
/* PCI config space reads/writes, to byte-word addressable memory. */
static uint64_t bw_conf1_read(void *opaque, hwaddr addr,
unsigned size)
{
PCIBus *b = opaque;
return pci_data_read(b, addr, size);
}
