static void gma_func0_init(struct device *dev)
{
u32 reg32;
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
pci_write_config32(dev, PCI_COMMAND, reg32);
/* configure GMBUSFREQ */
pci_update_config16(dev, 0xcc, ~0x1ff, 0xbc);
int vga_disable = (pci_read_config16(dev, D0F0_GGC) & 2) >> 1;
if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) {
if (vga_disable) {
printk(BIOS_INFO,
"IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n");
} else {
int lightup_ok;
gma_gfxinit(&lightup_ok);
}
} else {
pci_dev_init(dev);
}
intel_gma_restore_opregion();
}
static void nic_init(struct device *dev)
{
#if CONFIG_PCI_ROM_RUN == 1
pci_dev_init(dev);// it will init option rom
#endif
}
static void ide_init(struct device *dev)
{
/* Enable ide devices so the linux ide driver will work */
u32 dword;
u8 byte;
/* RPR10.1 disable MSI */
dword = pci_read_config32(dev, 0x70);
dword &= ~(1 << 16);
pci_write_config32(dev, 0x70, dword);
/* Enable UDMA on all devices, it will become UDMA0 (default PIO is PIO0) */
byte = pci_read_config8(dev, 0x54);
byte |= 0xf;
pci_write_config8(dev, 0x54, byte);
/* Enable I/O Access&& Bus Master */
dword = pci_read_config16(dev, 0x4);
dword |= 1 << 2;
pci_write_config16(dev, 0x4, dword);
#if CONFIG_PCI_ROM_RUN == 1
pci_dev_init(dev);
#endif
}
static void vga_init(device_t dev)
{
printk(BIOS_INFO, "Starting Graphics Initialization\n");
struct cbfs_file *file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "mbi.bin");
void *mbi = NULL;
unsigned int mbi_len = 0;
if (file) {
if (ntohl(file->type) != CBFS_TYPE_MBI) {
printk(BIOS_INFO, "CBFS: MBI binary is of type %x instead of"
"type %x\n", file->type, CBFS_TYPE_MBI);
} else {
mbi = (void *) CBFS_SUBHEADER(file);
mbi_len = ntohl(file->len);
}
} else {
printk(BIOS_INFO, "Could not find MBI.\n");
}
if (mbi && mbi_len) {
/* The GDT or coreboot table is going to live here. But
* a long time after we relocated the GNVS, so this is
* not troublesome.
*/
*(u32 *)0x500 = (u32)mbi;
*(u32 *)0x504 = (u32)mbi_len;
outb(0xeb, 0xb2);
}
pci_dev_init(dev);
printk(BIOS_INFO, "Graphics Initialization Complete\n");
/* Enable TV-Out */
#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
#define PIPE_A_CRT (1 << 0)
#define PIPE_A_LFP (1 << 1)
#define PIPE_A_TV (1 << 3)
#define PIPE_B_CRT (1 << 8)
#define PIPE_B_TV (1 << 10)
printk(BIOS_DEBUG, "Enabling TV-Out\n");
void runInt10(void);
X86_AX = 0x5f64;
X86_BX = 0x0001; // Set Display Device, force execution
X86_CX = PIPE_A_CRT | PIPE_A_TV;
// M.x86.R_CX = PIPE_B_TV;
runInt10();
switch (X86_AX) {
case 0x005f:
printk(BIOS_DEBUG, "... failed.\n");
break;
case 0x015f:
printk(BIOS_DEBUG, "... ok.\n");
break;
default:
printk(BIOS_DEBUG, "... not supported.\n");
break;
}
#endif
}
static void vga_init(device_t dev)
{
u8 reg8;
mainboard_interrupt_handlers(0x15, &via_cn700_int15_handler);
#undef OLD_BOCHS_METHOD
#ifdef OLD_BOCHS_METHOD
printk(BIOS_DEBUG, "Copying BOCHS BIOS to 0xf000\n");
/*
* Copy BOCHS BIOS from 4G-CONFIG_ROM_SIZE-64k (in flash) to 0xf0000 (in RAM)
* This is for compatibility with the VGA ROM's BIOS callbacks.
*/
memcpy((void *)0xf0000, (const void *)(0xffffffff - CONFIG_ROM_SIZE - 0xffff), 0x10000);
#endif
/* Set memory rate to 200 MHz. */
outb(0x3d, CRTM_INDEX);
reg8 = inb(CRTM_DATA);
reg8 &= 0x0f;
reg8 |= (0x1 << 4);
outb(0x3d, CRTM_INDEX);
outb(reg8, CRTM_DATA);
/* Set framebuffer size. */
reg8 = (CONFIG_VIDEO_MB / 4);
outb(0x39, SR_INDEX);
outb(reg8, SR_DATA);
pci_write_config8(dev, 0x04, 0x07);
pci_write_config8(dev, 0x0d, 0x20);
pci_write_config32(dev, 0x10, 0xf4000008);
pci_write_config32(dev, 0x14, 0xfb000000);
printk(BIOS_DEBUG, "Initializing VGA...\n");
pci_dev_init(dev);
/* It's not clear if these need to be programmed before or after
* the VGA BIOS runs. Try both, clean up later. */
/* Set memory rate to 200 MHz (again). */
outb(0x3d, CRTM_INDEX);
reg8 = inb(CRTM_DATA);
reg8 &= 0x0f;
reg8 |= (0x1 << 4);
outb(0x3d, CRTM_INDEX);
outb(reg8, CRTM_DATA);
/* Set framebuffer size (again). */
reg8 = (CONFIG_VIDEO_MB / 4);
outb(0x39, SR_INDEX);
outb(reg8, SR_DATA);
#ifdef OLD_BOCHS_METHOD
/* Clear the BOCHS BIOS out of memory, so it doesn't confuse Linux. */
memset((void *)0xf0000, 0, 0x10000);
#endif
}
static void gma_func0_init(struct device *dev)
{
u32 reg32;
/* IGD needs to be bus master. */
reg32 = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
pci_dev_init(dev);
}
static void qemu_init(device_t dev)
{
/* The VGA OPROM already lives at 0xc0000,
* force coreboot to use it.
*/
dev->on_mainboard = 1;
/* Now do the usual initialization */
pci_dev_init(dev);
}
static void gfx_init(device_t dev)
{
/* Pre VBIOS Init */
gfx_pre_vbios_init(dev);
/* Power Management Init */
gfx_pm_init(dev);
gfx_panel_setup(dev);
/* Run VBIOS */
pci_dev_init(dev);
/* Post VBIOS Init */
gfx_post_vbios_init(dev);
}
static void gma_func0_init(struct device *dev)
{
u32 reg32;
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
pci_write_config32(dev, PCI_COMMAND, reg32);
/* Init graphics power management */
gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
struct northbridge_intel_gm45_config *conf = dev->chip_info;
if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) {
/* PCI Init, will run VBIOS */
pci_dev_init(dev);
}
/* Post VBIOS init */
gma_pm_init_post_vbios(dev);
if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) {
u32 physbase;
struct resource *lfb_res;
struct resource *pio_res;
lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2);
pio_res = find_resource(dev, PCI_BASE_ADDRESS_4);
physbase = pci_read_config32(dev, 0x5c) & ~0xf;
if (gtt_res && gtt_res->base && physbase && pio_res
&& pio_res->base && lfb_res && lfb_res->base) {
printk(BIOS_SPEW,
"Initializing VGA without OPROM. MMIO 0x%llx\n",
gtt_res->base);
intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase,
pio_res->base, lfb_res->base);
}
/* Linux relies on VBT for panel info. */
generate_fake_intel_oprom(&conf->gfx, dev,
"$VBT IRONLAKE-MOBILE");
}
}
static void vga_init(device_t dev)
{
printk(BIOS_INFO, "Starting Graphics Initialization\n");
size_t mbi_len;
void *mbi = cbfs_boot_map_with_leak("mbi.bin", CBFS_TYPE_MBI, &mbi_len);
if (mbi && mbi_len) {
/* The GDT or coreboot table is going to live here. But
* a long time after we relocated the GNVS, so this is
* not troublesome.
*/
*(u32 *)0x500 = (u32)mbi;
*(u32 *)0x504 = (u32)mbi_len;
outb(0xeb, 0xb2);
}
pci_dev_init(dev);
printk(BIOS_INFO, "Graphics Initialization Complete\n");
/* Enable TV-Out */
#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
#define PIPE_A_CRT (1 << 0)
#define PIPE_A_LFP (1 << 1)
#define PIPE_A_TV (1 << 3)
#define PIPE_B_CRT (1 << 8)
#define PIPE_B_TV (1 << 10)
printk(BIOS_DEBUG, "Enabling TV-Out\n");
void runInt10(void);
X86_AX = 0x5f64;
X86_BX = 0x0001; // Set Display Device, force execution
X86_CX = PIPE_A_CRT | PIPE_A_TV;
// M.x86.R_CX = PIPE_B_TV;
runInt10();
switch (X86_AX) {
case 0x005f:
printk(BIOS_DEBUG, "... failed.\n");
break;
case 0x015f:
printk(BIOS_DEBUG, "... ok.\n");
break;
default:
printk(BIOS_DEBUG, "... not supported.\n");
break;
}
#endif
}
static void vga_init(device_t dev)
{
uint8_t reg8;
mainboard_interrupt_handlers(0x15, &via_vx800_int15_handler);
//A20 OPEN
reg8 = inb(0x92);
reg8 = reg8 | 2;
outb(reg8, 0x92);
//*
//pci_write_config8(dev, 0x04, 0x07);
//pci_write_config32(dev,0x10, 0xa0000008);
//pci_write_config32(dev,0x14, 0xdd000000);
pci_write_config32(dev, 0x10, VIACONFIG_VGA_PCI_10);
pci_write_config32(dev, 0x14, VIACONFIG_VGA_PCI_14);
pci_write_config8(dev, 0x3c, 0x0a); //same with vx855_lpc.c
//*/
printk(BIOS_DEBUG, "Initializing VGA...\n");
pci_dev_init(dev);
printk(BIOS_DEBUG, "Enable VGA console\n");
vga_enable_console();
if ((acpi_sleep_type == 3)/* || (PAYLOAD_IS_SEABIOS == 0)*/) {
/* It's not clear if these need to be programmed before or after
* the VGA bios runs. Try both, clean up later */
/* Set memory rate to 200MHz */
outb(0x3d, CRTM_INDEX);
reg8 = inb(CRTM_DATA);
reg8 &= 0x0f;
reg8 |= (0x3 << 4);
outb(0x3d, CRTM_INDEX);
outb(reg8, CRTM_DATA);
#if 0
/* Set framebuffer size to CONFIG_VIDEO_MB mb */
reg8 = (CONFIG_VIDEO_MB/4);
outb(0x39, SR_INDEX);
outb(reg8, SR_DATA);
#endif
}
}
static void gfx_init(struct device *dev)
{
/* Pre VBIOS Init */
gfx_pre_vbios_init(dev);
/* Power Management Init */
gfx_pm_init(dev);
gfx_panel_setup(dev);
/* Run VBIOS */
pci_dev_init(dev);
/* Post VBIOS Init */
gfx_post_vbios_init(dev);
/* Restore opregion on S3 resume */
intel_gma_restore_opregion();
}
static void gma_func0_init(struct device *dev)
{
u32 reg32;
/* Unconditionally reset graphics */
pci_write_config8(dev, GDRST, 1);
udelay(50);
pci_write_config8(dev, GDRST, 0);
/* wait for device to finish */
while (pci_read_config8(dev, GDRST) & 1) { };
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
/* PCI Init, will run VBIOS */
pci_dev_init(dev);
#endif
#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
/* This should probably run before post VBIOS init. */
printk(BIOS_SPEW, "Initializing VGA without OPROM.\n");
u32 iobase, mmiobase, graphics_base;
iobase = dev->resource_list[1].base;
mmiobase = dev->resource_list[0].base;
graphics_base = dev->resource_list[2].base + 0x20000;
printk(BIOS_SPEW, "GMADR=0x%08x GTTADR=0x%08x\n",
pci_read_config32(dev, GMADR),
pci_read_config32(dev, GTTADR)
);
int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx);
u32 uma_memory_base = pci_read_config32(dev, BSM) & ~((1 << 20) - 1);
int lightup_ok = i915lightup(uma_memory_base, iobase, mmiobase, graphics_base);
if (lightup_ok)
gfx_set_init_done(1);
#endif
}
static void igd_init(struct device *dev)
{
if (IS_ENABLED(CONFIG_GOP_SUPPORT))
return;
/* IGD needs to be Bus Master */
u32 reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
pci_write_config32(dev, PCI_COMMAND, reg32);
gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (!gtt_res || !gtt_res->base)
return;
/* Wait for any configured pre-graphics delay */
if (!acpi_is_wakeup_s3()) {
#if IS_ENABLED(CONFIG_CHROMEOS)
if (developer_mode_enabled() || recovery_mode_enabled() ||
vboot_wants_oprom())
mdelay(CONFIG_PRE_GRAPHICS_DELAY);
#else
mdelay(CONFIG_PRE_GRAPHICS_DELAY);
#endif
}
/* Initialize PCI device, load/execute BIOS Option ROM */
pci_dev_init(dev);
#if IS_ENABLED(CONFIG_CHROMEOS)
if (!gfx_get_init_done() && !acpi_is_wakeup_s3()) {
/*
* Enable DDI-A if the Option ROM did not execute:
*
* bit 0: Display detected (RO)
* bit 4: DDI A supports 4 lanes and DDI E is not used
* bit 7: DDI buffer is idle
*/
gtt_write(DDI_BUF_CTL_A, DDI_BUF_IS_IDLE | DDI_A_4_LANES |
DDI_INIT_DISPLAY_DETECTED);
}
#endif
}
static void gma_func0_init(struct device *dev)
{
u16 reg16;
u32 reg32;
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
pci_write_config32(dev, PCI_COMMAND, reg32);
/* configure GMBUSFREQ */
reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x2, 0)), 0xcc);
reg16 &= ~0x1ff;
reg16 |= 0xbc;
pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x2, 0)), 0xcc, reg16);
if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT))
native_init(dev);
else
pci_dev_init(dev);
}
static void gma_func0_init(struct device *dev)
{
u32 reg32;
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
pci_write_config32(dev, PCI_COMMAND, reg32);
/* Init graphics power management */
gma_pm_init_pre_vbios(dev);
if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT))
/* PCI Init, will run VBIOS */
pci_dev_init(dev);
/* Post VBIOS init */
gma_pm_init_post_vbios(dev);
int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1;
/* Running graphics init on S3 breaks Linux drm driver. */
if (!acpi_is_wakeup_s3() &&
CONFIG(MAINBOARD_USE_LIBGFXINIT)) {
if (vga_disable) {
printk(BIOS_INFO,
"IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n");
} else {
/* This should probably run before post VBIOS init. */
printk(BIOS_SPEW, "Initializing VGA without OPROM.\n");
int lightup_ok;
gma_gfxinit(&lightup_ok);
if (lightup_ok)
gfx_set_init_done(1);
}
}
gma_enable_swsci();
intel_gma_restore_opregion();
}
static void ide_init(struct device *dev)
{
struct southbridge_amd_sb700_config *conf;
/* Enable ide devices so the linux ide driver will work */
u32 dword;
u8 byte;
conf = dev->chip_info;
/* RPR9.1 disable MSI */
/* TODO: For A14, it should set as 1. I doubt it. */
dword = pci_read_config32(dev, 0x70);
dword &= ~(1 << 16);
pci_write_config32(dev, 0x70, dword);
/* Enable UDMA on all devices, it will become UDMA0 (default PIO is PIO0) */
byte = pci_read_config8(dev, 0x54);
byte |= 0xf;
pci_write_config8(dev, 0x54, byte);
/* Enable I/O Access&& Bus Master */
dword = pci_read_config16(dev, 0x4);
dword |= 1 << 2;
pci_write_config16(dev, 0x4, dword);
/* set ide as primary, if you want to boot from IDE, you'd better set it
* in $vendor/$mainboard/devicetree.cb */
if (conf->boot_switch_sata_ide == 1) {
struct device *sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
byte = pci_read_config8(sm_dev, 0xAD);
byte |= 1 << 4;
pci_write_config8(sm_dev, 0xAD, byte);
}
#if CONFIG_PCI_ROM_RUN == 1
pci_dev_init(dev);
#endif
}
static void vga_init(device_t dev)
{
u8 reg8;
mainboard_interrupt_handlers(0x15, &via_cx700_int15_handler);
//*
pci_write_config8(dev, 0x04, 0x07);
pci_write_config8(dev, 0x3e, 0x02);
pci_write_config8(dev, 0x0d, 0x40);
pci_write_config32(dev, 0x10, 0xa0000008);
pci_write_config32(dev, 0x14, 0xdd000000);
pci_write_config8(dev, 0x3c, 0x0b);
//*/
printk(BIOS_DEBUG, "Initializing VGA...\n");
pci_dev_init(dev);
if (pci_read_config32(dev, PCI_ROM_ADDRESS) != 0xc0000) return;
printk(BIOS_DEBUG, "Enable VGA console\n");
vga_enable_console();
/* It's not clear if these need to be programmed before or after
* the VGA bios runs. Try both, clean up later */
/* Set memory rate to 200MHz */
outb(0x3d, CRTM_INDEX);
reg8 = inb(CRTM_DATA);
reg8 &= 0x0f;
reg8 |= (0x3 << 4);
outb(0x3d, CRTM_INDEX);
outb(reg8, CRTM_DATA);
/* Set framebuffer size to 32mb */
reg8 = (32 / 4);
outb(0x39, SR_INDEX);
outb(reg8, SR_DATA);
}
static void ide_init(struct device *dev)
{
struct southbridge_nvidia_ck804_config *conf;
u32 dword;
u16 word;
u8 byte;
conf = dev->chip_info;
word = pci_read_config16(dev, 0x50);
/* Ensure prefetch is disabled. */
word &= ~((1 << 15) | (1 << 13));
if (conf->ide1_enable) {
/* Enable secondary IDE interface. */
word |= (1 << 0);
printk(BIOS_DEBUG, "IDE1 \t");
}
if (conf->ide0_enable) {
/* Enable primary IDE interface. */
word |= (1 << 1);
printk(BIOS_DEBUG, "IDE0\n");
}
word |= (1 << 12);
word |= (1 << 14);
pci_write_config16(dev, 0x50, word);
byte = 0x20; /* Latency: 64 --> 32 */
pci_write_config8(dev, 0xd, byte);
dword = pci_read_config32(dev, 0xf8);
dword |= 12;
pci_write_config32(dev, 0xf8, dword);
#if CONFIG_PCI_ROM_RUN
pci_dev_init(dev);
#endif
}
int main(int argc,char *argv[]) {
unsigned int bus,slot,func;
ioport_reg(PCI_CONFIG_DATA);
ioport_reg(PCI_CONFIG_ADDRESS);
devfs_init();
for (bus=0;bus<PCI_MAXBUSSES;bus++) {
for (slot=0;slot<PCI_MAXSLOTS;slot++) {
for (func=0;func<PCI_MAXFUNCS;func++) {
int vendor = pci_config_readd(bus,slot,func,0)&0x0000FFFF;
if (vendor!=0x0000 && vendor!=0xFFFF) {
if (pci_dev_init(bus,slot,func)==-1) fprintf(stderr,"pci: Could not create device for: pci%d.%d.%d\n",bus,slot,func);
}
}
}
}
devfs_mainloop();
return 0;
}
static void ide_init(struct device *dev)
{
struct southbridge_amd_sb800_config *conf;
/* Enable ide devices so the linux ide driver will work */
u32 dword;
u8 byte;
conf = dev->chip_info;
/* RPR9.1 disable MSI */
/* TODO: For A14, it should set as 1. I doubt it. */
dword = pci_read_config32(dev, 0x70);
dword &= ~(1 << 16);
pci_write_config32(dev, 0x70, dword);
/* Ultra DMA mode */
/* enable UDMA */
byte = pci_read_config8(dev, 0x54);
byte |= 1 << 0;
pci_write_config8(dev, 0x54, byte);
/* Enable I/O Access&& Bus Master */
dword = pci_read_config16(dev, 0x4);
dword |= 1 << 2;
pci_write_config16(dev, 0x4, dword);
/* set ide as primary, if you want to boot from IDE, you'd better set it
* in mainboard/Config.lb */
if (conf->boot_switch_sata_ide == 1) {
byte = pci_read_config8(dev, 0xAD);
byte |= 1 << 4;
pci_write_config8(dev, 0xAD, byte);
}
#if CONFIG_PCI_ROM_RUN == 1
pci_dev_init(dev);
#endif
}
static void gma_func0_init(struct device *dev)
{
u32 reg32;
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
pci_write_config32(dev, PCI_COMMAND, reg32);
if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) {
/* PCI Init, will run VBIOS */
pci_dev_init(dev);
} else {
u32 physbase;
struct resource *pio_res;
struct northbridge_intel_pineview_config *conf = dev->chip_info;
/* Find base addresses */
mmio_res = find_resource(dev, 0x10);
gtt_res = find_resource(dev, 0x1c);
pio_res = find_resource(dev, 0x14);
physbase = pci_read_config32(dev, 0x5c) & ~0xf;
if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base) {
printk(BIOS_SPEW, "Initializing VGA. MMIO 0x%llx\n",
mmio_res->base);
intel_gma_init(conf, dev, res2mmio(mmio_res, 0, 0),
res2mmio(gtt_res, 0, 0),
physbase, pio_res->base);
}
/* Linux relies on VBT for panel info. */
generate_fake_intel_oprom(&conf->gfx, dev,
"$VBT PINEVIEW ");
}
}
static void ide_init(struct device *dev)
{
struct southbridge_sis_sis966_config *conf;
/* Enable ide devices so the linux ide driver will work */
uint32_t dword;
uint16_t word;
uint8_t byte;
conf = dev->chip_info;
print_debug("IDE_INIT:---------->\n");
//-------------- enable IDE (SiS5513) -------------------------
{
uint8_t temp8;
int i=0;
while(SiS_SiS5513_init[i][0] != 0)
{
temp8 = pci_read_config8(dev, SiS_SiS5513_init[i][0]);
temp8 &= SiS_SiS5513_init[i][1];
temp8 |= SiS_SiS5513_init[i][2];
pci_write_config8(dev, SiS_SiS5513_init[i][0], temp8);
i++;
};
}
//-----------------------------------------------------------
word = pci_read_config16(dev, 0x50);
/* Ensure prefetch is disabled */
word &= ~((1 << 15) | (1 << 13));
if (conf->ide1_enable) {
/* Enable secondary ide interface */
word |= (1<<0);
printk(BIOS_DEBUG, "IDE1 \t");
}
if (conf->ide0_enable) {
/* Enable primary ide interface */
word |= (1<<1);
printk(BIOS_DEBUG, "IDE0\n");
}
word |= (1<<12);
word |= (1<<14);
pci_write_config16(dev, 0x50, word);
byte = 0x20 ; // Latency: 64-->32
pci_write_config8(dev, 0xd, byte);
dword = pci_read_config32(dev, 0xf8);
dword |= 12;
pci_write_config32(dev, 0xf8, dword);
#if CONFIG_PCI_ROM_RUN
pci_dev_init(dev);
#endif
#if DEBUG_IDE
{
int i;
print_debug("****** IDE PCI config ******");
print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C");
for(i=0;i<0xff;i+=4){
if((i%16)==0){
print_debug("\n");
print_debug_hex8(i);
print_debug(": ");
}
print_debug_hex32(pci_read_config32(dev,i));
print_debug(" ");
}
print_debug("\n");
}
#endif
print_debug("IDE_INIT:<----------\n");
}