static int __init cpcihp_generic_init(void) { int status; struct resource *r; struct pci_dev *dev; info(DRIVER_DESC " version: " DRIVER_VERSION); status = validate_parameters(); if (status) return status; r = request_region(port, 1, "#ENUM hotswap signal register"); if (!r) return -EBUSY; dev = pci_get_domain_bus_and_slot(0, bridge_busnr, PCI_DEVFN(bridge_slot, 0)); if (!dev || dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { err("Invalid bridge device %s", bridge); pci_dev_put(dev); return -EINVAL; } bus = dev->subordinate; pci_dev_put(dev); memset(&generic_hpc, 0, sizeof (struct cpci_hp_controller)); generic_hpc.ops = &generic_hpc_ops; status = cpci_hp_register_controller(&generic_hpc); if (status != 0) { err("Could not register cPCI hotplug controller"); return -ENODEV; } dbg("registered controller"); status = cpci_hp_register_bus(bus, first_slot, last_slot); if (status != 0) { err("Could not register cPCI hotplug bus"); goto init_bus_register_error; } dbg("registered bus"); status = cpci_hp_start(); if (status != 0) { err("Could not started cPCI hotplug system"); goto init_start_error; } dbg("started cpci hp system"); return 0; init_start_error: cpci_hp_unregister_bus(bus); init_bus_register_error: cpci_hp_unregister_controller(&generic_hpc); err("status = %d", status); return status; }
static inline void CDV_MSG_WRITE32(int domain, uint port, uint offset, u32 value) { int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0; struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0); pci_write_config_dword(pci_root, 0xD4, value); pci_write_config_dword(pci_root, 0xD0, mcr); pci_dev_put(pci_root); }
static inline u32 CDV_MSG_READ32(int domain, uint port, uint offset) { int mcr = (0x10<<24) | (port << 16) | (offset << 8); uint32_t ret_val = 0; struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0); pci_write_config_dword(pci_root, 0xD0, mcr); pci_read_config_dword(pci_root, 0xD4, &ret_val); pci_dev_put(pci_root); return ret_val; }
static void mid_get_vbt_data(struct drm_psb_private *dev_priv) { struct drm_device *dev = dev_priv->dev; u32 addr; u8 __iomem *vbt_virtual; struct mid_vbt_header vbt_header; struct pci_dev *pci_gfx_root = pci_get_domain_bus_and_slot(pci_domain_nr(dev->pdev->bus), 0, PCI_DEVFN(2, 0)); int ret = -1; /* Get the address of the platform config vbt */ pci_read_config_dword(pci_gfx_root, 0xFC, &addr); pci_dev_put(pci_gfx_root); dev_dbg(dev->dev, "drm platform config address is %x\n", addr); if (!addr) goto out; /* get the virtual address of the vbt */ vbt_virtual = ioremap(addr, sizeof(vbt_header)); if (!vbt_virtual) goto out; memcpy_fromio(&vbt_header, vbt_virtual, sizeof(vbt_header)); iounmap(vbt_virtual); if (memcmp(&vbt_header.signature, "$GCT", 4)) goto out; dev_dbg(dev->dev, "GCT revision is %02x\n", vbt_header.revision); switch (vbt_header.revision) { case 0x00: ret = mid_get_vbt_data_r0(dev_priv, addr); break; case 0x01: ret = mid_get_vbt_data_r1(dev_priv, addr); break; case 0x10: ret = mid_get_vbt_data_r10(dev_priv, addr); break; default: dev_err(dev->dev, "Unknown revision of GCT!\n"); } out: if (ret) dev_err(dev->dev, "Unable to read GCT!"); else dev_priv->has_gct = true; }
static void cper_print_pcie(const char *pfx, const struct cper_sec_pcie *pcie, const struct acpi_hest_generic_data *gdata) { #ifdef CONFIG_ACPI_APEI_PCIEAER struct pci_dev *dev; #endif if (pcie->validation_bits & CPER_PCIE_VALID_PORT_TYPE) printk("%s""port_type: %d, %s\n", pfx, pcie->port_type, pcie->port_type < ARRAY_SIZE(cper_pcie_port_type_strs) ? cper_pcie_port_type_strs[pcie->port_type] : "unknown"); if (pcie->validation_bits & CPER_PCIE_VALID_VERSION) printk("%s""version: %d.%d\n", pfx, pcie->version.major, pcie->version.minor); if (pcie->validation_bits & CPER_PCIE_VALID_COMMAND_STATUS) printk("%s""command: 0x%04x, status: 0x%04x\n", pfx, pcie->command, pcie->status); if (pcie->validation_bits & CPER_PCIE_VALID_DEVICE_ID) { const __u8 *p; printk("%s""device_id: %04x:%02x:%02x.%x\n", pfx, pcie->device_id.segment, pcie->device_id.bus, pcie->device_id.device, pcie->device_id.function); printk("%s""slot: %d\n", pfx, pcie->device_id.slot >> CPER_PCIE_SLOT_SHIFT); printk("%s""secondary_bus: 0x%02x\n", pfx, pcie->device_id.secondary_bus); printk("%s""vendor_id: 0x%04x, device_id: 0x%04x\n", pfx, pcie->device_id.vendor_id, pcie->device_id.device_id); p = pcie->device_id.class_code; printk("%s""class_code: %02x%02x%02x\n", pfx, p[0], p[1], p[2]); } if (pcie->validation_bits & CPER_PCIE_VALID_SERIAL_NUMBER) printk("%s""serial number: 0x%04x, 0x%04x\n", pfx, pcie->serial_number.lower, pcie->serial_number.upper); if (pcie->validation_bits & CPER_PCIE_VALID_BRIDGE_CONTROL_STATUS) printk( "%s""bridge: secondary_status: 0x%04x, control: 0x%04x\n", pfx, pcie->bridge.secondary_status, pcie->bridge.control); #ifdef CONFIG_ACPI_APEI_PCIEAER dev = pci_get_domain_bus_and_slot(pcie->device_id.segment, pcie->device_id.bus, pcie->device_id.function); if (!dev) { pr_err("PCI AER Cannot get PCI device %04x:%02x:%02x.%d\n", pcie->device_id.segment, pcie->device_id.bus, pcie->device_id.slot, pcie->device_id.function); return; } if (pcie->validation_bits & CPER_PCIE_VALID_AER_INFO) cper_print_aer(pfx, dev, gdata->error_severity, (struct aer_capability_regs *) pcie->aer_info); pci_dev_put(dev); #endif }
SYSCALL_DEFINE5(pciconfig_write, unsigned long, bus, unsigned long, dfn, unsigned long, off, unsigned long, len, void __user *, buf) { struct pci_dev *dev; u8 byte; u16 word; u32 dword; int err = 0; if (!capable(CAP_SYS_ADMIN)) return -EPERM; dev = pci_get_domain_bus_and_slot(0, bus, dfn); if (!dev) return -ENODEV; switch (len) { case 1: err = get_user(byte, (u8 __user *)buf); if (err) break; err = pci_user_write_config_byte(dev, off, byte); if (err != PCIBIOS_SUCCESSFUL) err = -EIO; break; case 2: err = get_user(word, (u16 __user *)buf); if (err) break; err = pci_user_write_config_word(dev, off, word); if (err != PCIBIOS_SUCCESSFUL) err = -EIO; break; case 4: err = get_user(dword, (u32 __user *)buf); if (err) break; err = pci_user_write_config_dword(dev, off, dword); if (err != PCIBIOS_SUCCESSFUL) err = -EIO; break; default: err = -EINVAL; break; } pci_dev_put(dev); return err; }
/* * Get the revison ID, B0:D2:F0;0x08 */ static void mid_get_pci_revID(struct drm_psb_private *dev_priv) { uint32_t platform_rev_id = 0; int domain = pci_domain_nr(dev_priv->dev->pdev->bus); struct pci_dev *pci_gfx_root = pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(2, 0)); if (pci_gfx_root == NULL) { WARN_ON(1); return; } pci_read_config_dword(pci_gfx_root, 0x08, &platform_rev_id); dev_priv->platform_rev_id = (uint8_t) platform_rev_id; pci_dev_put(pci_gfx_root); dev_dbg(dev_priv->dev->dev, "platform_rev_id is %x\n", dev_priv->platform_rev_id); }
void gma_get_core_freq(struct drm_device *dev) { uint32_t clock; struct pci_dev *pci_root = pci_get_domain_bus_and_slot(pci_domain_nr(dev->pdev->bus), 0, 0); struct drm_psb_private *dev_priv = dev->dev_private; /*pci_write_config_dword(pci_root, 0xD4, 0x00C32004);*/ /*pci_write_config_dword(pci_root, 0xD0, 0xE0033000);*/ pci_write_config_dword(pci_root, 0xD0, 0xD0050300); pci_read_config_dword(pci_root, 0xD4, &clock); pci_dev_put(pci_root); switch (clock & 0x07) { case 0: dev_priv->core_freq = 100; break; case 1: dev_priv->core_freq = 133; break; case 2: dev_priv->core_freq = 150; break; case 3: dev_priv->core_freq = 178; break; case 4: dev_priv->core_freq = 200; break; case 5: case 6: case 7: dev_priv->core_freq = 266; break; default: dev_priv->core_freq = 0; } }
static int xgbe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct xgbe_prv_data *pdata; struct device *dev = &pdev->dev; void __iomem * const *iomap_table; struct pci_dev *rdev; unsigned int ma_lo, ma_hi; unsigned int reg; int bar_mask; int ret; pdata = xgbe_alloc_pdata(dev); if (IS_ERR(pdata)) { ret = PTR_ERR(pdata); goto err_alloc; } pdata->pcidev = pdev; pci_set_drvdata(pdev, pdata); /* Get the version data */ pdata->vdata = (struct xgbe_version_data *)id->driver_data; ret = pcim_enable_device(pdev); if (ret) { dev_err(dev, "pcim_enable_device failed\n"); goto err_pci_enable; } /* Obtain the mmio areas for the device */ bar_mask = pci_select_bars(pdev, IORESOURCE_MEM); ret = pcim_iomap_regions(pdev, bar_mask, XGBE_DRV_NAME); if (ret) { dev_err(dev, "pcim_iomap_regions failed\n"); goto err_pci_enable; } iomap_table = pcim_iomap_table(pdev); if (!iomap_table) { dev_err(dev, "pcim_iomap_table failed\n"); ret = -ENOMEM; goto err_pci_enable; } pdata->xgmac_regs = iomap_table[XGBE_XGMAC_BAR]; if (!pdata->xgmac_regs) { dev_err(dev, "xgmac ioremap failed\n"); ret = -ENOMEM; goto err_pci_enable; } pdata->xprop_regs = pdata->xgmac_regs + XGBE_MAC_PROP_OFFSET; pdata->xi2c_regs = pdata->xgmac_regs + XGBE_I2C_CTRL_OFFSET; if (netif_msg_probe(pdata)) { dev_dbg(dev, "xgmac_regs = %p\n", pdata->xgmac_regs); dev_dbg(dev, "xprop_regs = %p\n", pdata->xprop_regs); dev_dbg(dev, "xi2c_regs = %p\n", pdata->xi2c_regs); } pdata->xpcs_regs = iomap_table[XGBE_XPCS_BAR]; if (!pdata->xpcs_regs) { dev_err(dev, "xpcs ioremap failed\n"); ret = -ENOMEM; goto err_pci_enable; } if (netif_msg_probe(pdata)) dev_dbg(dev, "xpcs_regs = %p\n", pdata->xpcs_regs); /* Set the PCS indirect addressing definition registers */ rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0)); if (rdev && (rdev->vendor == PCI_VENDOR_ID_AMD) && (rdev->device == 0x15d0)) { pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF; pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT; } else { pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF; pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT; } pci_dev_put(rdev); /* Configure the PCS indirect addressing support */ reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg); pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET); pdata->xpcs_window <<= 6; pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE); pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7); pdata->xpcs_window_mask = pdata->xpcs_window_size - 1; if (netif_msg_probe(pdata)) { dev_dbg(dev, "xpcs window def = %#010x\n", pdata->xpcs_window_def_reg); dev_dbg(dev, "xpcs window sel = %#010x\n", pdata->xpcs_window_sel_reg); dev_dbg(dev, "xpcs window = %#010x\n", pdata->xpcs_window); dev_dbg(dev, "xpcs window size = %#010x\n", pdata->xpcs_window_size); dev_dbg(dev, "xpcs window mask = %#010x\n", pdata->xpcs_window_mask); } pci_set_master(pdev); /* Enable all interrupts in the hardware */ XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff); /* Retrieve the MAC address */ ma_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO); ma_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI); pdata->mac_addr[0] = ma_lo & 0xff; pdata->mac_addr[1] = (ma_lo >> 8) & 0xff; pdata->mac_addr[2] = (ma_lo >> 16) & 0xff; pdata->mac_addr[3] = (ma_lo >> 24) & 0xff; pdata->mac_addr[4] = ma_hi & 0xff; pdata->mac_addr[5] = (ma_hi >> 8) & 0xff; if (!XP_GET_BITS(ma_hi, XP_MAC_ADDR_HI, VALID) || !is_valid_ether_addr(pdata->mac_addr)) { dev_err(dev, "invalid mac address\n"); ret = -EINVAL; goto err_pci_enable; } /* Clock settings */ pdata->sysclk_rate = XGBE_V2_DMA_CLOCK_FREQ; pdata->ptpclk_rate = XGBE_V2_PTP_CLOCK_FREQ; /* Set the DMA coherency values */ pdata->coherent = 1; pdata->arcr = XGBE_DMA_PCI_ARCR; pdata->awcr = XGBE_DMA_PCI_AWCR; pdata->awarcr = XGBE_DMA_PCI_AWARCR; /* Set the maximum channels and queues */ reg = XP_IOREAD(pdata, XP_PROP_1); pdata->tx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_DMA); pdata->rx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_DMA); pdata->tx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_QUEUES); pdata->rx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_QUEUES); if (netif_msg_probe(pdata)) { dev_dbg(dev, "max tx/rx channel count = %u/%u\n", pdata->tx_max_channel_count, pdata->tx_max_channel_count); dev_dbg(dev, "max tx/rx hw queue count = %u/%u\n", pdata->tx_max_q_count, pdata->rx_max_q_count); } /* Set the hardware channel and queue counts */ xgbe_set_counts(pdata); /* Set the maximum fifo amounts */ reg = XP_IOREAD(pdata, XP_PROP_2); pdata->tx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, TX_FIFO_SIZE); pdata->tx_max_fifo_size *= 16384; pdata->tx_max_fifo_size = min(pdata->tx_max_fifo_size, pdata->vdata->tx_max_fifo_size); pdata->rx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, RX_FIFO_SIZE); pdata->rx_max_fifo_size *= 16384; pdata->rx_max_fifo_size = min(pdata->rx_max_fifo_size, pdata->vdata->rx_max_fifo_size); if (netif_msg_probe(pdata)) dev_dbg(dev, "max tx/rx max fifo size = %u/%u\n", pdata->tx_max_fifo_size, pdata->rx_max_fifo_size); /* Configure interrupt support */ ret = xgbe_config_irqs(pdata); if (ret) goto err_pci_enable; /* Configure the netdev resource */ ret = xgbe_config_netdev(pdata); if (ret) goto err_irq_vectors; netdev_notice(pdata->netdev, "net device enabled\n"); return 0; err_irq_vectors: pci_free_irq_vectors(pdata->pcidev); err_pci_enable: xgbe_free_pdata(pdata); err_alloc: dev_notice(dev, "net device not enabled\n"); return ret; }
static void mid_get_fuse_settings(struct drm_device *dev) { struct drm_psb_private *dev_priv = dev->dev_private; struct pci_dev *pci_root = pci_get_domain_bus_and_slot(pci_domain_nr(dev->pdev->bus), 0, 0); uint32_t fuse_value = 0; uint32_t fuse_value_tmp = 0; #define FB_REG06 0xD0810600 #define FB_MIPI_DISABLE (1 << 11) #define FB_REG09 0xD0810900 #define FB_SKU_MASK 0x7000 #define FB_SKU_SHIFT 12 #define FB_SKU_100 0 #define FB_SKU_100L 1 #define FB_SKU_83 2 if (pci_root == NULL) { WARN_ON(1); return; } pci_write_config_dword(pci_root, 0xD0, FB_REG06); pci_read_config_dword(pci_root, 0xD4, &fuse_value); /* FB_MIPI_DISABLE doesn't mean LVDS on with Medfield */ if (IS_MRST(dev)) dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE; DRM_INFO("internal display is %s\n", dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display"); /* Prevent runtime suspend at start*/ if (dev_priv->iLVDS_enable) { dev_priv->is_lvds_on = true; dev_priv->is_mipi_on = false; } else { dev_priv->is_mipi_on = true; dev_priv->is_lvds_on = false; } dev_priv->video_device_fuse = fuse_value; pci_write_config_dword(pci_root, 0xD0, FB_REG09); pci_read_config_dword(pci_root, 0xD4, &fuse_value); dev_dbg(dev->dev, "SKU values is 0x%x.\n", fuse_value); fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT; dev_priv->fuse_reg_value = fuse_value; switch (fuse_value_tmp) { case FB_SKU_100: dev_priv->core_freq = 200; break; case FB_SKU_100L: dev_priv->core_freq = 100; break; case FB_SKU_83: dev_priv->core_freq = 166; break; default: dev_warn(dev->dev, "Invalid SKU values, SKU value = 0x%08x\n", fuse_value_tmp); dev_priv->core_freq = 0; } dev_dbg(dev->dev, "LNC core clk is %dMHz.\n", dev_priv->core_freq); pci_dev_put(pci_root); }
SYSCALL_DEFINE5(pciconfig_read, unsigned long, bus, unsigned long, dfn, unsigned long, off, unsigned long, len, void __user *, buf) { struct pci_dev *dev; u8 byte; u16 word; u32 dword; long err; long cfg_ret; if (!capable(CAP_SYS_ADMIN)) return -EPERM; err = -ENODEV; dev = pci_get_domain_bus_and_slot(0, bus, dfn); if (!dev) goto error; switch (len) { case 1: cfg_ret = pci_user_read_config_byte(dev, off, &byte); break; case 2: cfg_ret = pci_user_read_config_word(dev, off, &word); break; case 4: cfg_ret = pci_user_read_config_dword(dev, off, &dword); break; default: err = -EINVAL; goto error; } err = -EIO; if (cfg_ret != PCIBIOS_SUCCESSFUL) goto error; switch (len) { case 1: err = put_user(byte, (unsigned char __user *)buf); break; case 2: err = put_user(word, (unsigned short __user *)buf); break; case 4: err = put_user(dword, (unsigned int __user *)buf); break; } pci_dev_put(dev); return err; error: /* ??? XFree86 doesn't even check the return value. They just look for 0xffffffff in the output, since that's what they get instead of a machine check on x86. */ switch (len) { case 1: put_user(-1, (unsigned char __user *)buf); break; case 2: put_user(-1, (unsigned short __user *)buf); break; case 4: put_user(-1, (unsigned int __user *)buf); break; } pci_dev_put(dev); return err; }