/* Config the VIA chip */
void mpc85xx_config_via(struct pci_controller *hose,
pci_dev_t dev, struct pci_config_table *tab)
{
pci_dev_t bridge;
unsigned int cmdstat;
/* Enable USB and IDE functions */
pci_hose_write_config_byte(hose, dev, 0x48, 0x08);
pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY| PCI_COMMAND_MASTER;
pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
/*
* Force the backplane P2P bridge to have a window
* open from 0x00000000-0x00001fff in PCI I/O space.
* This allows legacy I/O (i8259, etc) on the VIA
* southbridge to be accessed.
*/
bridge = PCI_BDF(0,BRIDGE_ID,0);
pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0);
pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0);
pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10);
pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0);
}
void pci_init_board(void)
{
struct pci_controller *hose;
fsl_pcie_init_board(0);
hose = find_hose_by_cfg_addr((void *)(CONFIG_SYS_PCIE3_ADDR));
if (hose) {
u32 temp32;
u8 uli_busno = hose->first_busno + 2;
/*
* Activate ULI1575 legacy chip by performing a fake
* memory access. Needed to make ULI RTC work.
* Device 1d has the first on-board memory BAR.
*/
pci_hose_read_config_dword(hose, PCI_BDF(uli_busno, 0x1d, 0),
PCI_BASE_ADDRESS_1, &temp32);
if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
void *p = pci_mem_to_virt(PCI_BDF(uli_busno, 0x1d, 0),
temp32, 4, 0);
debug(" uli1572 read to %p\n", p);
in_be32(p);
}
}
}
unsigned int x86_pci_read_config32(pci_dev_t dev, unsigned where)
{
uint32_t value;
pci_hose_read_config_dword(get_hose(), dev, where, &value);
return value;
}
void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
struct pci_config_table *entry)
{
unsigned int cmdstat = 0;
pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
/* always enable io space on vga boards */
pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
cmdstat |= PCI_COMMAND_IO;
pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
}
static void pciauto_prescan_setup_bridge(struct pci_controller *hose,
pci_dev_t dev, int sub_bus)
{
struct pci_region *pci_mem = hose->pci_mem;
struct pci_region *pci_io = hose->pci_io;
unsigned int cmdstat;
pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
/* Configure bus number registers */
pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev));
pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus);
pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
if (pci_mem) {
/* Round memory allocator to 1MB boundary */
pciauto_region_align(pci_mem, 0x100000);
/* Set up memory and I/O filter limits, assume 32-bit I/O space */
pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
(pci_mem->bus_lower & 0xfff00000) >> 16);
cmdstat |= PCI_COMMAND_MEMORY;
}
if (pci_io) {
/* Round I/O allocator to 4KB boundary */
pciauto_region_align(pci_io, 0x1000);
pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
(pci_io->bus_lower & 0x0000f000) >> 8);
pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
(pci_io->bus_lower & 0xffff0000) >> 16);
cmdstat |= PCI_COMMAND_IO;
}
/* We don't support prefetchable memory for now, so disable */
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000);
/* Enable memory and I/O accesses, enable bus master */
pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
}
static void pciauto_prescan_setup_bridge(struct pci_controller *hose,
pci_dev_t dev, int sub_bus)
{
struct pci_region *pci_mem = hose->pci_mem;
struct pci_region *pci_prefetch = hose->pci_prefetch;
struct pci_region *pci_io = hose->pci_io;
unsigned int cmdstat;
pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
/* Configure bus number registers */
pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev));
pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus);
pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
if (pci_mem) {
/* Round memory allocator to 1MB boundary */
pciauto_region_align(pci_mem, 0x100000);
/* Set up memory and I/O filter limits, assume 32-bit I/O space */
pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
(pci_mem->bus_lower & 0xfff00000) >> 16);
cmdstat |= PCI_COMMAND_MEMORY;
}
if (pci_prefetch) {
/* Round memory allocator to 1MB boundary */
pciauto_region_align(pci_prefetch, 0x100000);
/* Set up memory and I/O filter limits, assume 32-bit I/O space */
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
(pci_prefetch->bus_lower & 0xfff00000) >> 16);
cmdstat |= PCI_COMMAND_MEMORY;
} else {
int pci_hose_config_device(struct pci_controller *hose,
pci_dev_t dev,
unsigned long io,
pci_addr_t mem,
unsigned long command)
{
u32 bar_response;
unsigned int old_command;
pci_addr_t bar_value;
pci_size_t bar_size;
unsigned char pin;
int bar, found_mem64;
debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io,
(u64)mem, command);
pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);
for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
pci_hose_read_config_dword(hose, dev, bar, &bar_response);
if (!bar_response)
continue;
found_mem64 = 0;
/* Check the BAR type and set our address mask */
if (bar_response & PCI_BASE_ADDRESS_SPACE) {
bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
/* round up region base address to a multiple of size */
io = ((io - 1) | (bar_size - 1)) + 1;
bar_value = io;
/* compute new region base address */
io = io + bar_size;
} else {
if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
PCI_BASE_ADDRESS_MEM_TYPE_64) {
u32 bar_response_upper;
u64 bar64;
pci_hose_write_config_dword(hose, dev, bar + 4,
0xffffffff);
pci_hose_read_config_dword(hose, dev, bar + 4,
&bar_response_upper);
bar64 = ((u64)bar_response_upper << 32) | bar_response;
bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
found_mem64 = 1;
} else {
bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
}
/* round up region base address to multiple of size */
mem = ((mem - 1) | (bar_size - 1)) + 1;
bar_value = mem;
/* compute new region base address */
mem = mem + bar_size;
}
/* Write it out and update our limit */
pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
if (found_mem64) {
bar += 4;
#ifdef CONFIG_SYS_PCI_64BIT
pci_hose_write_config_dword(hose, dev, bar,
(u32)(bar_value >> 32));
#else
pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
#endif
}
}
/* Configure Cache Line Size Register */
pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
/* Configure Latency Timer */
pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
/* Disable interrupt line, if device says it wants to use interrupts */
pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
if (pin != 0) {
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
PCI_INTERRUPT_LINE_DISABLE);
}
pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
(old_command & 0xffff0000) | command);
return 0;
}
void pciauto_setup_device(struct pci_controller *hose,
pci_dev_t dev, int bars_num,
struct pci_region *mem,
struct pci_region *io)
{
unsigned int bar_value, bar_response, bar_size;
unsigned int cmdstat = 0;
struct pci_region *bar_res;
int bar, bar_nr = 0;
int found_mem64 = 0;
pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) {
/* Tickle the BAR and get the response */
pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
pci_hose_read_config_dword(hose, dev, bar, &bar_response);
/* If BAR is not implemented go to the next BAR */
if (!bar_response)
continue;
found_mem64 = 0;
/* Check the BAR type and set our address mask */
if (bar_response & PCI_BASE_ADDRESS_SPACE) {
bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
bar_res = io;
DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%x, ", bar_nr, bar_size);
} else {
if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
PCI_BASE_ADDRESS_MEM_TYPE_64)
found_mem64 = 1;
bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
bar_res = mem;
DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%x, ", bar_nr, bar_size);
}
if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
/* Write it out and update our limit */
pci_hose_write_config_dword(hose, dev, bar, bar_value);
/*
* If we are a 64-bit decoder then increment to the
* upper 32 bits of the bar and force it to locate
* in the lower 4GB of memory.
*/
if (found_mem64) {
bar += 4;
pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
}
cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
}
DEBUGF("\n");
bar_nr++;
}
pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
}
void pciauto_setup_device(struct pci_controller *hose,
pci_dev_t dev, int bars_num,
struct pci_region *mem,
struct pci_region *prefetch,
struct pci_region *io)
{
u32 bar_response;
pci_size_t bar_size;
u16 cmdstat = 0;
int bar, bar_nr = 0;
#ifndef CONFIG_PCI_ENUM_ONLY
pci_addr_t bar_value;
struct pci_region *bar_res;
int found_mem64 = 0;
#endif
pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
for (bar = PCI_BASE_ADDRESS_0;
bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
/* Tickle the BAR and get the response */
#ifndef CONFIG_PCI_ENUM_ONLY
pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
#endif
pci_hose_read_config_dword(hose, dev, bar, &bar_response);
/* If BAR is not implemented go to the next BAR */
if (!bar_response)
continue;
#ifndef CONFIG_PCI_ENUM_ONLY
found_mem64 = 0;
#endif
/* Check the BAR type and set our address mask */
if (bar_response & PCI_BASE_ADDRESS_SPACE) {
bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
& 0xffff) + 1;
#ifndef CONFIG_PCI_ENUM_ONLY
bar_res = io;
#endif
DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", bar_nr, (u64)bar_size);
} else {
if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
PCI_BASE_ADDRESS_MEM_TYPE_64) {
u32 bar_response_upper;
u64 bar64;
#ifndef CONFIG_PCI_ENUM_ONLY
pci_hose_write_config_dword(hose, dev, bar + 4,
0xffffffff);
#endif
pci_hose_read_config_dword(hose, dev, bar + 4,
&bar_response_upper);
bar64 = ((u64)bar_response_upper << 32) | bar_response;
bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
#ifndef CONFIG_PCI_ENUM_ONLY
found_mem64 = 1;
#endif
} else {
bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
}
#ifndef CONFIG_PCI_ENUM_ONLY
if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
bar_res = prefetch;
else
bar_res = mem;
#endif
DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%llx, ", bar_nr, (u64)bar_size);
}
#ifndef CONFIG_PCI_ENUM_ONLY
if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
/* Write it out and update our limit */
pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
if (found_mem64) {
bar += 4;
#ifdef CONFIG_SYS_PCI_64BIT
pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
#else
/*
* If we are a 64-bit decoder then increment to the
* upper 32 bits of the bar and force it to locate
* in the lower 4GB of memory.
*/
pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
#endif
}
}
#endif
cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
DEBUGF("\n");
bar_nr++;
}
void pci_init_board(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
struct fsl_pci_info pci_info[3];
u32 devdisr, pordevsr, io_sel, temp32;
int first_free_busno = 0;
int num = 0;
int pcie_ep, pcie_configured;
devdisr = in_be32(&gur->devdisr);
pordevsr = in_be32(&gur->pordevsr);
io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
printf("eTSEC1 is in sgmii mode.\n");
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
printf("eTSEC2 is in sgmii mode.\n");
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
printf("eTSEC3 is in sgmii mode.\n");
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
printf("eTSEC4 is in sgmii mode.\n");
puts("\n");
#ifdef CONFIG_PCIE3
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
SET_STD_PCIE_INFO(pci_info[num], 3);
pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie3_hose, first_free_busno);
/*
* Activate ULI1575 legacy chip by performing a fake
* memory access. Needed to make ULI RTC work.
* Device 1d has the first on-board memory BAR.
*/
pci_hose_read_config_dword(&pcie3_hose, PCI_BDF(2, 0x1d, 0),
PCI_BASE_ADDRESS_1, &temp32);
if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
temp32, 4, 0);
debug(" uli1572 read to %p\n", p);
in_be32(p);
}
} else {
printf("PCIE3: disabled\n");
}
puts("\n");
#else
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
#endif
#ifdef CONFIG_PCIE2
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
SET_STD_PCIE_INFO(pci_info[num], 2);
pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie2_hose, first_free_busno);
} else {
printf("PCIE2: disabled\n");
}
puts("\n");
#else
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
#endif
#ifdef CONFIG_PCIE1
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
SET_STD_PCIE_INFO(pci_info[num], 1);
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
} else {
printf("PCIE1: disabled\n");
}
puts("\n");
#else
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
#endif
}
static void setup_pci_bar(unsigned int bus, unsigned int dev, unsigned func,
unsigned char header, struct ftpci100_data *priv)
{
struct pci_controller *hose = (struct pci_controller *)&local_hose;
unsigned int i, tmp32, bar_no, iovsmem = 1;
pci_dev_t dev_nu;
/* A device is present, add an entry to the array */
devs[priv->ndevs].bus = bus;
devs[priv->ndevs].dev = dev;
devs[priv->ndevs].func = func;
dev_nu = PCI_BDF(bus, dev, func);
if ((header & 0x7f) == 0x01)
/* PCI-PCI Bridge */
bar_no = 2;
else
bar_no = 6;
/* Allocate address spaces by configuring BARs */
for (i = 0; i < bar_no; i++) {
pci_hose_write_config_dword(hose, dev_nu,
PCI_BASE_ADDRESS_0 + i * 4, 0xffffffff);
pci_hose_read_config_dword(hose, dev_nu,
PCI_BASE_ADDRESS_0 + i * 4, &tmp32);
if (tmp32 == 0x0)
continue;
/* IO space */
if (tmp32 & 0x1) {
iovsmem = 0;
unsigned int size_mask = ~(tmp32 & 0xfffffffc);
if (priv->io_base & size_mask)
priv->io_base = (priv->io_base & ~size_mask) + \
size_mask + 1;
devs[priv->ndevs].bar[i].addr = priv->io_base;
devs[priv->ndevs].bar[i].size = size_mask + 1;
pci_hose_write_config_dword(hose, dev_nu,
PCI_BASE_ADDRESS_0 + i * 4,
priv->io_base);
debug("Allocated IO address 0x%X-" \
"0x%X for Bus %d, Device %d, Function %d\n",
priv->io_base,
priv->io_base + size_mask, bus, dev, func);
priv->io_base += size_mask + 1;
} else {
/* Memory space */
unsigned int is_64bit = ((tmp32 & 0x6) == 0x4);
unsigned int is_pref = tmp32 & 0x8;
unsigned int size_mask = ~(tmp32 & 0xfffffff0);
unsigned int alloc_base;
unsigned int *addr_mem_base;
if (is_pref)
addr_mem_base = &priv->mem_base;
else
addr_mem_base = &priv->mmio_base;
alloc_base = *addr_mem_base;
if (alloc_base & size_mask)
alloc_base = (alloc_base & ~size_mask) \
+ size_mask + 1;
pci_hose_write_config_dword(hose, dev_nu,
PCI_BASE_ADDRESS_0 + i * 4, alloc_base);
debug("Allocated %s address 0x%X-" \
"0x%X for Bus %d, Device %d, Function %d\n",
is_pref ? "MEM" : "MMIO", alloc_base,
alloc_base + size_mask, bus, dev, func);
devs[priv->ndevs].bar[i].addr = alloc_base;
devs[priv->ndevs].bar[i].size = size_mask + 1;
debug("BAR address BAR size\n");
debug("%010x %08d\n",
devs[priv->ndevs].bar[0].addr,
devs[priv->ndevs].bar[0].size);
alloc_base += size_mask + 1;
*addr_mem_base = alloc_base;
if (is_64bit) {
i++;
pci_hose_write_config_dword(hose, dev_nu,
PCI_BASE_ADDRESS_0 + i * 4, 0x0);
}
}
}
/* Enable Bus Master, Memory Space, and IO Space */
pci_hose_read_config_dword(hose, dev_nu, PCI_CACHE_LINE_SIZE, &tmp32);
pci_hose_write_config_dword(hose, dev_nu, PCI_CACHE_LINE_SIZE, 0x08);
pci_hose_read_config_dword(hose, dev_nu, PCI_CACHE_LINE_SIZE, &tmp32);
pci_hose_read_config_dword(hose, dev_nu, PCI_COMMAND, &tmp32);
tmp32 &= 0xffff;
if (iovsmem == 0)
tmp32 |= 0x5;
else
tmp32 |= 0x6;
pci_hose_write_config_dword(hose, dev_nu, PCI_COMMAND, tmp32);
}
static void pci_bus_scan(struct ftpci100_data *priv)
{
struct pci_controller *hose = (struct pci_controller *)&local_hose;
unsigned int bus, dev, func;
pci_dev_t dev_nu;
unsigned int data32;
unsigned int tmp;
unsigned char header;
unsigned char int_pin;
unsigned int niobars;
unsigned int nmbars;
priv->ndevs = 1;
nmbars = 0;
niobars = 0;
for (bus = 0; bus < MAX_BUS_NUM; bus++)
for (dev = 0; dev < MAX_DEV_NUM; dev++)
for (func = 0; func < MAX_FUN_NUM; func++) {
dev_nu = PCI_BDF(bus, dev, func);
pci_hose_read_config_dword(hose, dev_nu,
PCI_VENDOR_ID, &data32);
/*
* some broken boards return 0 or ~0,
* if a slot is empty.
*/
if (data32 == 0xffffffff ||
data32 == 0x00000000 ||
data32 == 0x0000ffff ||
data32 == 0xffff0000)
continue;
pci_hose_read_config_dword(hose, dev_nu,
PCI_HEADER_TYPE, &tmp);
header = (unsigned char)tmp;
setup_pci_bar(bus, dev, func, header, priv);
devs[priv->ndevs].v_id = (u16)(data32 & \
0x0000ffff);
devs[priv->ndevs].d_id = (u16)((data32 & \
0xffff0000) >> 16);
/* Figure out what INTX# line the card uses */
pci_hose_read_config_byte(hose, dev_nu,
PCI_INTERRUPT_PIN, &int_pin);
/* assign the appropriate irq line */
if (int_pin > PCI_IRQ_LINES) {
printf("more irq lines than expect\n");
} else if (int_pin != 0) {
/* This device uses an interrupt line */
devs[priv->ndevs].pin = int_pin;
}
pci_hose_read_config_dword(hose, dev_nu,
PCI_CLASS_DEVICE, &data32);
debug("%06d %03d %03d " \
"%04d %08x %08x " \
"%03d %08x %06d %08x\n",
priv->ndevs, devs[priv->ndevs].bus,
devs[priv->ndevs].dev,
devs[priv->ndevs].func,
devs[priv->ndevs].d_id,
devs[priv->ndevs].v_id,
devs[priv->ndevs].pin,
devs[priv->ndevs].bar[0].addr,
devs[priv->ndevs].bar[0].size,
data32 >> 8);
priv->ndevs++;
}
}
