static int
ciss_setup_msix(struct ciss_softc *sc)
{
int i, count, error;
i = ciss_lookup(sc->ciss_dev);
if (ciss_vendor_data[i].flags & CISS_BOARD_NOMSI)
return (EINVAL);
count = pci_msix_count(sc->ciss_dev);
if (count < CISS_MSI_COUNT) {
count = pci_msi_count(sc->ciss_dev);
if (count < CISS_MSI_COUNT)
return (EINVAL);
}
count = MIN(count, CISS_MSI_COUNT);
error = pci_alloc_msix(sc->ciss_dev, &count);
if (error) {
error = pci_alloc_msi(sc->ciss_dev, &count);
if (error)
return (EINVAL);
}
sc->ciss_msi = count;
for (i = 0; i < count; i++)
sc->ciss_irq_rid[i] = i + 1;
return (0);
}
/**
* Attempt to allocate MSI interrupts, returning the count in @p msi_count
* on success.
*/
static int
bhndb_pci_alloc_msi(struct bhndb_pci_softc *sc, int *msi_count)
{
int error, count;
/* Is MSI available? */
if (pci_msi_count(sc->parent) < BHNDB_PCI_MSI_COUNT)
return (ENXIO);
/* Allocate expected message count */
count = BHNDB_PCI_MSI_COUNT;
if ((error = pci_alloc_msi(sc->parent, &count))) {
device_printf(sc->dev, "failed to allocate MSI interrupts: "
"%d\n", error);
return (error);
}
if (count < BHNDB_PCI_MSI_COUNT) {
pci_release_msi(sc->parent);
return (ENXIO);
}
*msi_count = count;
return (0);
}
int
mpr_pci_setup_interrupts(struct mpr_softc *sc)
{
device_t dev;
int i, error, msgs;
dev = sc->mpr_dev;
error = ENXIO;
if ((sc->disable_msix == 0) &&
((msgs = pci_msix_count(dev)) >= MPR_MSI_COUNT))
error = mpr_alloc_msix(sc, MPR_MSI_COUNT);
if ((error != 0) && (sc->disable_msi == 0) &&
((msgs = pci_msi_count(dev)) >= MPR_MSI_COUNT))
error = mpr_alloc_msi(sc, MPR_MSI_COUNT);
if (error != 0) {
sc->mpr_flags |= MPR_FLAGS_INTX;
sc->mpr_irq_rid[0] = 0;
sc->mpr_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ,
&sc->mpr_irq_rid[0], RF_SHAREABLE | RF_ACTIVE);
if (sc->mpr_irq[0] == NULL) {
mpr_printf(sc, "Cannot allocate INTx interrupt\n");
return (ENXIO);
}
error = bus_setup_intr(dev, sc->mpr_irq[0],
INTR_TYPE_BIO | INTR_MPSAFE, NULL, mpr_intr, sc,
&sc->mpr_intrhand[0]);
if (error)
mpr_printf(sc, "Cannot setup INTx interrupt\n");
} else {
sc->mpr_flags |= MPR_FLAGS_MSI;
for (i = 0; i < MPR_MSI_COUNT; i++) {
sc->mpr_irq_rid[i] = i + 1;
sc->mpr_irq[i] = bus_alloc_resource_any(dev,
SYS_RES_IRQ, &sc->mpr_irq_rid[i], RF_ACTIVE);
if (sc->mpr_irq[i] == NULL) {
mpr_printf(sc,
"Cannot allocate MSI interrupt\n");
return (ENXIO);
}
error = bus_setup_intr(dev, sc->mpr_irq[i],
INTR_TYPE_BIO | INTR_MPSAFE, NULL, mpr_intr_msi,
sc, &sc->mpr_intrhand[i]);
if (error) {
mpr_printf(sc,
"Cannot setup MSI interrupt %d\n", i);
break;
}
}
}
return (error);
}
static int
vtpci_alloc_msi(struct vtpci_softc *sc)
{
device_t dev;
int nmsi, cnt;
dev = sc->vtpci_dev;
nmsi = pci_msi_count(dev);
if (nmsi < 1)
return (1);
cnt = 1;
if (pci_alloc_msi(dev, &cnt) == 0 && cnt == 1)
return (0);
return (1);
}
static int
vtpci_alloc_msi(struct vtpci_softc *sc)
{
device_t dev;
int nmsi, cnt, required;
dev = sc->vtpci_dev;
required = 1;
nmsi = pci_msi_count(dev);
if (nmsi < required)
return (1);
cnt = required;
if (pci_alloc_msi(dev, &cnt) == 0 && cnt >= required)
return (0);
pci_release_msi(dev);
return (1);
}
/*
* This function is used by device drivers like pci_intr_map().
*
* "ihps" is the array of vector numbers which MSI used instead of IRQ number.
* "count" must be power of 2.
* "count" can not decrease.
* If "count" struct intrsources cannot be allocated, return non-zero value.
*/
int
pci_msi_alloc_exact(const struct pci_attach_args *pa, pci_intr_handle_t **ihps,
int count)
{
int hw_max;
/* MSI vector count must be power of 2. */
KASSERT(count > 0);
KASSERT(((count - 1) & count) == 0);
hw_max = pci_msi_count(pa->pa_pc, pa->pa_tag);
if (hw_max == 0)
return ENODEV;
if (count > hw_max) {
DPRINTF(("over hardware max MSI count %d\n", hw_max));
return EINVAL;
}
return x86_pci_msi_alloc_exact(ihps, count, pa);
}
/*
* This function is used by device drivers like pci_intr_map().
*
* "ihps" is the array of vector numbers which MSI used instead of IRQ number.
* "count" must be power of 2.
* "count" can decrease if struct intrsource cannot be allocated.
* if count == 0, return non-zero value.
*/
int
pci_msi_alloc(const struct pci_attach_args *pa, pci_intr_handle_t **ihps,
int *count)
{
int hw_max;
/* MSI vector count must be power of 2. */
KASSERT(*count > 0);
KASSERT(((*count - 1) & *count) == 0);
hw_max = pci_msi_count(pa->pa_pc, pa->pa_tag);
if (hw_max == 0)
return ENODEV;
if (*count > hw_max) {
DPRINTF(("cut off MSI count to %d\n", hw_max));
*count = hw_max; /* cut off hw_max */
}
return x86_pci_msi_alloc(ihps, count, pa);
}
static int
uart_pci_attach(device_t dev)
{
struct uart_softc *sc;
int count;
sc = device_get_softc(dev);
/*
* Use MSI in preference to legacy IRQ if available.
* Whilst some PCIe UARTs support >1 MSI vector, use only the first.
*/
if (pci_msi_count(dev) > 0) {
count = 1;
if (pci_alloc_msi(dev, &count) == 0) {
sc->sc_irid = 1;
device_printf(dev, "Using %d MSI message\n", count);
}
}
return (uart_bus_attach(dev));
}
static int
sfxge_intr_setup_msi(struct sfxge_softc *sc)
{
struct sfxge_intr_hdl *table;
struct sfxge_intr *intr;
device_t dev;
int count;
int error;
dev = sc->dev;
intr = &sc->intr;
table = intr->table;
/*
* Check if MSI is available. All messages must be written to
* the same address and on x86 this means the IRQs have the
* same CPU affinity. So we only ever allocate 1.
*/
count = pci_msi_count(dev) ? 1 : 0;
if (count == 0)
return (EINVAL);
if ((error = pci_alloc_msi(dev, &count)) != 0)
return (ENOMEM);
/* Allocate interrupt handler. */
if (sfxge_intr_alloc(sc, count) != 0) {
pci_release_msi(dev);
return (ENOMEM);
}
intr->type = EFX_INTR_MESSAGE;
intr->n_alloc = count;
return (0);
}
static int
mpt_pci_attach(device_t dev)
{
struct mpt_softc *mpt;
int iqd;
uint32_t data, cmd;
int mpt_io_bar, mpt_mem_bar;
mpt = (struct mpt_softc*)device_get_softc(dev);
switch (pci_get_device(dev)) {
case MPI_MANUFACTPAGE_DEVICEID_FC909_FB:
case MPI_MANUFACTPAGE_DEVICEID_FC909:
case MPI_MANUFACTPAGE_DEVICEID_FC919:
case MPI_MANUFACTPAGE_DEVICEID_FC919_LAN_FB:
case MPI_MANUFACTPAGE_DEVICEID_FC929:
case MPI_MANUFACTPAGE_DEVICEID_FC929_LAN_FB:
case MPI_MANUFACTPAGE_DEVICEID_FC929X:
case MPI_MANUFACTPAGE_DEVICEID_FC929X_LAN_FB:
case MPI_MANUFACTPAGE_DEVICEID_FC919X:
case MPI_MANUFACTPAGE_DEVICEID_FC919X_LAN_FB:
case MPI_MANUFACTPAGE_DEVICEID_FC949E:
case MPI_MANUFACTPAGE_DEVICEID_FC949X:
mpt->is_fc = 1;
break;
case MPI_MANUFACTPAGE_DEVID_SAS1078:
case MPI_MANUFACTPAGE_DEVID_SAS1078DE_FB:
mpt->is_1078 = 1;
/* FALLTHROUGH */
case MPI_MANUFACTPAGE_DEVID_SAS1064:
case MPI_MANUFACTPAGE_DEVID_SAS1064A:
case MPI_MANUFACTPAGE_DEVID_SAS1064E:
case MPI_MANUFACTPAGE_DEVID_SAS1066:
case MPI_MANUFACTPAGE_DEVID_SAS1066E:
case MPI_MANUFACTPAGE_DEVID_SAS1068:
case MPI_MANUFACTPAGE_DEVID_SAS1068A_FB:
case MPI_MANUFACTPAGE_DEVID_SAS1068E:
case MPI_MANUFACTPAGE_DEVID_SAS1068E_FB:
mpt->is_sas = 1;
break;
default:
mpt->is_spi = 1;
break;
}
mpt->dev = dev;
mpt->unit = device_get_unit(dev);
mpt->raid_resync_rate = MPT_RAID_RESYNC_RATE_DEFAULT;
mpt->raid_mwce_setting = MPT_RAID_MWCE_DEFAULT;
mpt->raid_queue_depth = MPT_RAID_QUEUE_DEPTH_DEFAULT;
mpt->verbose = MPT_PRT_NONE;
mpt->role = MPT_ROLE_NONE;
mpt->mpt_ini_id = MPT_INI_ID_NONE;
#ifdef __sparc64__
if (mpt->is_spi)
mpt->mpt_ini_id = OF_getscsinitid(dev);
#endif
mpt_set_options(mpt);
if (mpt->verbose == MPT_PRT_NONE) {
mpt->verbose = MPT_PRT_WARN;
/* Print INFO level (if any) if bootverbose is set */
mpt->verbose += (bootverbose != 0)? 1 : 0;
}
/* Make sure memory access decoders are enabled */
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
if ((cmd & PCIM_CMD_MEMEN) == 0) {
device_printf(dev, "Memory accesses disabled");
return (ENXIO);
}
/*
* Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER are set.
*/
cmd |=
PCIM_CMD_SERRESPEN | PCIM_CMD_PERRESPEN |
PCIM_CMD_BUSMASTEREN | PCIM_CMD_MWRICEN;
pci_write_config(dev, PCIR_COMMAND, cmd, 2);
/*
* Make sure we've disabled the ROM.
*/
data = pci_read_config(dev, PCIR_BIOS, 4);
data &= ~PCIM_BIOS_ENABLE;
pci_write_config(dev, PCIR_BIOS, data, 4);
/*
* Is this part a dual?
* If so, link with our partner (around yet)
*/
switch (pci_get_device(dev)) {
case MPI_MANUFACTPAGE_DEVICEID_FC929:
case MPI_MANUFACTPAGE_DEVICEID_FC929_LAN_FB:
case MPI_MANUFACTPAGE_DEVICEID_FC949E:
case MPI_MANUFACTPAGE_DEVICEID_FC949X:
case MPI_MANUFACTPAGE_DEVID_53C1030:
case MPI_MANUFACTPAGE_DEVID_53C1030ZC:
mpt_link_peer(mpt);
break;
default:
break;
}
/*
* Figure out which are the I/O and MEM Bars
*/
data = pci_read_config(dev, PCIR_BAR(0), 4);
if (PCI_BAR_IO(data)) {
/* BAR0 is IO, BAR1 is memory */
mpt_io_bar = 0;
mpt_mem_bar = 1;
} else {
/* BAR0 is memory, BAR1 is IO */
mpt_mem_bar = 0;
mpt_io_bar = 1;
}
/*
* Set up register access. PIO mode is required for
* certain reset operations (but must be disabled for
* some cards otherwise).
*/
mpt_io_bar = PCIR_BAR(mpt_io_bar);
mpt->pci_pio_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
&mpt_io_bar, RF_ACTIVE);
if (mpt->pci_pio_reg == NULL) {
if (bootverbose) {
device_printf(dev,
"unable to map registers in PIO mode\n");
}
} else {
mpt->pci_pio_st = rman_get_bustag(mpt->pci_pio_reg);
mpt->pci_pio_sh = rman_get_bushandle(mpt->pci_pio_reg);
}
mpt_mem_bar = PCIR_BAR(mpt_mem_bar);
mpt->pci_reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
&mpt_mem_bar, RF_ACTIVE);
if (mpt->pci_reg == NULL) {
if (bootverbose || mpt->is_sas || mpt->pci_pio_reg == NULL) {
device_printf(dev,
"Unable to memory map registers.\n");
}
if (mpt->is_sas || mpt->pci_pio_reg == NULL) {
device_printf(dev, "Giving Up.\n");
goto bad;
}
if (bootverbose) {
device_printf(dev, "Falling back to PIO mode.\n");
}
mpt->pci_st = mpt->pci_pio_st;
mpt->pci_sh = mpt->pci_pio_sh;
} else {
mpt->pci_st = rman_get_bustag(mpt->pci_reg);
mpt->pci_sh = rman_get_bushandle(mpt->pci_reg);
}
/* Get a handle to the interrupt */
iqd = 0;
if (mpt->msi_enable) {
/*
* First try to alloc an MSI-X message. If that
* fails, then try to alloc an MSI message instead.
*/
if (pci_msix_count(dev) == 1) {
mpt->pci_msi_count = 1;
if (pci_alloc_msix(dev, &mpt->pci_msi_count) == 0) {
iqd = 1;
} else {
mpt->pci_msi_count = 0;
}
}
if (iqd == 0 && pci_msi_count(dev) == 1) {
mpt->pci_msi_count = 1;
if (pci_alloc_msi(dev, &mpt->pci_msi_count) == 0) {
iqd = 1;
} else {
mpt->pci_msi_count = 0;
}
}
}
mpt->pci_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &iqd,
RF_ACTIVE | (mpt->pci_msi_count ? 0 : RF_SHAREABLE));
if (mpt->pci_irq == NULL) {
device_printf(dev, "could not allocate interrupt\n");
goto bad;
}
MPT_LOCK_SETUP(mpt);
/* Disable interrupts at the part */
mpt_disable_ints(mpt);
/* Register the interrupt handler */
if (mpt_setup_intr(dev, mpt->pci_irq, MPT_IFLAGS, NULL, mpt_pci_intr,
mpt, &mpt->ih)) {
device_printf(dev, "could not setup interrupt\n");
goto bad;
}
/* Allocate dma memory */
if (mpt_dma_mem_alloc(mpt)) {
mpt_prt(mpt, "Could not allocate DMA memory\n");
goto bad;
}
#if 0
/*
* Save the PCI config register values
*
* Hard resets are known to screw up the BAR for diagnostic
* memory accesses (Mem1).
*
* Using Mem1 is known to make the chip stop responding to
* configuration space transfers, so we need to save it now
*/
mpt_read_config_regs(mpt);
#endif
/*
* Disable PIO until we need it
*/
if (mpt->is_sas) {
pci_disable_io(dev, SYS_RES_IOPORT);
}
/* Initialize the hardware */
if (mpt->disabled == 0) {
if (mpt_attach(mpt) != 0) {
goto bad;
}
} else {
mpt_prt(mpt, "device disabled at user request\n");
goto bad;
}
mpt->eh = EVENTHANDLER_REGISTER(shutdown_post_sync, mpt_pci_shutdown,
dev, SHUTDOWN_PRI_DEFAULT);
if (mpt->eh == NULL) {
mpt_prt(mpt, "shutdown event registration failed\n");
(void) mpt_detach(mpt);
goto bad;
}
return (0);
bad:
mpt_dma_mem_free(mpt);
mpt_free_bus_resources(mpt);
mpt_unlink_peer(mpt);
MPT_LOCK_DESTROY(mpt);
/*
* but return zero to preserve unit numbering
*/
return (0);
}
int
ppt_setup_msi(struct vm *vm, int vcpu, int bus, int slot, int func,
uint64_t addr, uint64_t msg, int numvec)
{
int i, rid, flags;
int msi_count, startrid, error, tmp;
struct pptdev *ppt;
if (numvec < 0 || numvec > MAX_MSIMSGS)
return (EINVAL);
ppt = ppt_find(bus, slot, func);
if (ppt == NULL)
return (ENOENT);
if (ppt->vm != vm) /* Make sure we own this device */
return (EBUSY);
/* Free any allocated resources */
ppt_teardown_msi(ppt);
if (numvec == 0) /* nothing more to do */
return (0);
flags = RF_ACTIVE;
msi_count = pci_msi_count(ppt->dev);
if (msi_count == 0) {
startrid = 0; /* legacy interrupt */
msi_count = 1;
flags |= RF_SHAREABLE;
} else
startrid = 1; /* MSI */
/*
* The device must be capable of supporting the number of vectors
* the guest wants to allocate.
*/
if (numvec > msi_count)
return (EINVAL);
/*
* Make sure that we can allocate all the MSI vectors that are needed
* by the guest.
*/
if (startrid == 1) {
tmp = numvec;
error = pci_alloc_msi(ppt->dev, &tmp);
if (error)
return (error);
else if (tmp != numvec) {
pci_release_msi(ppt->dev);
return (ENOSPC);
} else {
/* success */
}
}
ppt->msi.startrid = startrid;
/*
* Allocate the irq resource and attach it to the interrupt handler.
*/
for (i = 0; i < numvec; i++) {
ppt->msi.num_msgs = i + 1;
ppt->msi.cookie[i] = NULL;
rid = startrid + i;
ppt->msi.res[i] = bus_alloc_resource_any(ppt->dev, SYS_RES_IRQ,
&rid, flags);
if (ppt->msi.res[i] == NULL)
break;
ppt->msi.arg[i].pptdev = ppt;
ppt->msi.arg[i].addr = addr;
ppt->msi.arg[i].msg_data = msg + i;
error = bus_setup_intr(ppt->dev, ppt->msi.res[i],
INTR_TYPE_NET | INTR_MPSAFE,
pptintr, NULL, &ppt->msi.arg[i],
&ppt->msi.cookie[i]);
if (error != 0)
break;
}
if (i < numvec) {
ppt_teardown_msi(ppt);
return (ENXIO);
}
return (0);
}
static int
siba_bwn_msi_count(device_t dev, device_t child)
{
return (pci_msi_count(dev));
}
/*
* Allocate resources for our device, set up the bus interface.
*/
static int
aac_pci_attach(device_t dev)
{
struct aac_softc *sc;
const struct aac_ident *id;
int count, error, reg, rid;
fwprintf(NULL, HBA_FLAGS_DBG_FUNCTION_ENTRY_B, "");
/*
* Initialise softc.
*/
sc = device_get_softc(dev);
sc->aac_dev = dev;
/* assume failure is 'not configured' */
error = ENXIO;
/*
* Verify that the adapter is correctly set up in PCI space.
*/
pci_enable_busmaster(dev);
if (!(pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_BUSMASTEREN)) {
device_printf(dev, "can't enable bus-master feature\n");
goto out;
}
/*
* Allocate the PCI register window(s).
*/
rid = PCIR_BAR(0);
if ((sc->aac_regs_res0 = bus_alloc_resource_any(dev,
SYS_RES_MEMORY, &rid, RF_ACTIVE)) == NULL) {
device_printf(dev, "can't allocate register window 0\n");
goto out;
}
sc->aac_btag0 = rman_get_bustag(sc->aac_regs_res0);
sc->aac_bhandle0 = rman_get_bushandle(sc->aac_regs_res0);
if (sc->aac_hwif == AAC_HWIF_NARK) {
rid = PCIR_BAR(1);
if ((sc->aac_regs_res1 = bus_alloc_resource_any(dev,
SYS_RES_MEMORY, &rid, RF_ACTIVE)) == NULL) {
device_printf(dev,
"can't allocate register window 1\n");
goto out;
}
sc->aac_btag1 = rman_get_bustag(sc->aac_regs_res1);
sc->aac_bhandle1 = rman_get_bushandle(sc->aac_regs_res1);
} else {
sc->aac_regs_res1 = sc->aac_regs_res0;
sc->aac_btag1 = sc->aac_btag0;
sc->aac_bhandle1 = sc->aac_bhandle0;
}
/*
* Allocate the interrupt.
*/
rid = 0;
count = 0;
if (aac_enable_msi != 0 && pci_find_cap(dev, PCIY_MSI, ®) == 0) {
count = pci_msi_count(dev);
if (count > 1)
count = 1;
else
count = 0;
if (count == 1 && pci_alloc_msi(dev, &count) == 0)
rid = 1;
}
if ((sc->aac_irq = bus_alloc_resource_any(sc->aac_dev, SYS_RES_IRQ,
&rid, RF_ACTIVE | (count != 0 ? 0 : RF_SHAREABLE))) == NULL) {
device_printf(dev, "can't allocate interrupt\n");
goto out;
}
/*
* Allocate the parent bus DMA tag appropriate for our PCI interface.
*
* Note that some of these controllers are 64-bit capable.
*/
if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
PAGE_SIZE, 0, /* algnmnt, boundary */
BUS_SPACE_MAXADDR, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
BUS_SPACE_UNRESTRICTED, /* nsegments */
BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
0, /* flags */
NULL, NULL, /* No locking needed */
&sc->aac_parent_dmat)) {
device_printf(dev, "can't allocate parent DMA tag\n");
goto out;
}
/*
* Detect the hardware interface version, set up the bus interface
* indirection.
*/
id = aac_find_ident(dev);
sc->aac_hwif = id->hwif;
switch(sc->aac_hwif) {
case AAC_HWIF_I960RX:
case AAC_HWIF_NARK:
fwprintf(sc, HBA_FLAGS_DBG_INIT_B, "set hardware up for i960Rx/NARK");
sc->aac_if = &aac_rx_interface;
break;
case AAC_HWIF_STRONGARM:
fwprintf(sc, HBA_FLAGS_DBG_INIT_B, "set hardware up for StrongARM");
sc->aac_if = &aac_sa_interface;
break;
case AAC_HWIF_RKT:
fwprintf(sc, HBA_FLAGS_DBG_INIT_B, "set hardware up for Rocket/MIPS");
sc->aac_if = &aac_rkt_interface;
break;
default:
sc->aac_hwif = AAC_HWIF_UNKNOWN;
device_printf(dev, "unknown hardware type\n");
error = ENXIO;
goto out;
}
/* Set up quirks */
sc->flags = id->quirks;
/*
* Do bus-independent initialisation.
*/
error = aac_attach(sc);
out:
if (error)
aac_free(sc);
return(error);
}
static int
malo_pci_attach(device_t dev)
{
int error = ENXIO, i, msic, reg;
struct malo_pci_softc *psc = device_get_softc(dev);
struct malo_softc *sc = &psc->malo_sc;
sc->malo_dev = dev;
pci_enable_busmaster(dev);
/*
* Setup memory-mapping of PCI registers.
*/
psc->malo_mem_spec = malo_res_spec_mem;
error = bus_alloc_resources(dev, psc->malo_mem_spec, psc->malo_res_mem);
if (error) {
device_printf(dev, "couldn't allocate memory resources\n");
return (ENXIO);
}
/*
* Arrange and allocate interrupt line.
*/
sc->malo_invalid = 1;
if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
msic = pci_msi_count(dev);
if (bootverbose)
device_printf(dev, "MSI count : %d\n", msic);
} else
msic = 0;
psc->malo_irq_spec = malo_res_spec_legacy;
if (msic == MALO_MSI_MESSAGES && msi_disable == 0) {
if (pci_alloc_msi(dev, &msic) == 0) {
if (msic == MALO_MSI_MESSAGES) {
device_printf(dev, "Using %d MSI messages\n",
msic);
psc->malo_irq_spec = malo_res_spec_msi;
psc->malo_msi = 1;
} else
pci_release_msi(dev);
}
}
error = bus_alloc_resources(dev, psc->malo_irq_spec, psc->malo_res_irq);
if (error) {
device_printf(dev, "couldn't allocate IRQ resources\n");
goto bad;
}
if (psc->malo_msi == 0)
error = bus_setup_intr(dev, psc->malo_res_irq[0],
INTR_TYPE_NET | INTR_MPSAFE, malo_intr, NULL, sc,
&psc->malo_intrhand[0]);
else {
for (i = 0; i < MALO_MSI_MESSAGES; i++) {
error = bus_setup_intr(dev, psc->malo_res_irq[i],
INTR_TYPE_NET | INTR_MPSAFE, malo_intr, NULL, sc,
&psc->malo_intrhand[i]);
if (error != 0)
break;
}
}
/*
* Setup DMA descriptor area.
*/
if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1, 0, /* alignment, bounds */
BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
BUS_SPACE_MAXADDR, /* maxsize */
0, /* nsegments */
BUS_SPACE_MAXADDR, /* maxsegsize */
0, /* flags */
NULL, /* lockfunc */
NULL, /* lockarg */
&sc->malo_dmat)) {
device_printf(dev, "cannot allocate DMA tag\n");
goto bad1;
}
sc->malo_io0t = rman_get_bustag(psc->malo_res_mem[0]);
sc->malo_io0h = rman_get_bushandle(psc->malo_res_mem[0]);
sc->malo_io1t = rman_get_bustag(psc->malo_res_mem[1]);
sc->malo_io1h = rman_get_bushandle(psc->malo_res_mem[1]);
error = malo_attach(pci_get_device(dev), sc);
if (error != 0)
goto bad2;
return (error);
bad2:
bus_dma_tag_destroy(sc->malo_dmat);
bad1:
if (psc->malo_msi == 0)
bus_teardown_intr(dev, psc->malo_res_irq[0],
psc->malo_intrhand[0]);
else {
for (i = 0; i < MALO_MSI_MESSAGES; i++)
bus_teardown_intr(dev, psc->malo_res_irq[i],
psc->malo_intrhand[i]);
}
bus_release_resources(dev, psc->malo_irq_spec, psc->malo_res_irq);
bad:
if (psc->malo_msi != 0)
pci_release_msi(dev);
bus_release_resources(dev, psc->malo_mem_spec, psc->malo_res_mem);
return (error);
}
static int
ismt_attach(device_t dev)
{
struct ismt_softc *sc = device_get_softc(dev);
int err, num_vectors, val;
sc->pcidev = dev;
pci_enable_busmaster(dev);
if ((sc->smbdev = device_add_child(dev, "smbus", -1)) == NULL) {
device_printf(dev, "no smbus child found\n");
err = ENXIO;
goto fail;
}
sc->mmio_rid = PCIR_BAR(0);
sc->mmio_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
&sc->mmio_rid, RF_ACTIVE);
if (sc->mmio_res == NULL) {
device_printf(dev, "cannot allocate mmio region\n");
err = ENOMEM;
goto fail;
}
sc->mmio_tag = rman_get_bustag(sc->mmio_res);
sc->mmio_handle = rman_get_bushandle(sc->mmio_res);
/* Attach "smbus" child */
if ((err = bus_generic_attach(dev)) != 0) {
device_printf(dev, "failed to attach child: %d\n", err);
err = ENXIO;
goto fail;
}
bus_dma_tag_create(bus_get_dma_tag(dev), 4, PAGE_SIZE,
BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
DESC_SIZE, 1, DESC_SIZE,
0, NULL, NULL, &sc->desc_dma_tag);
bus_dma_tag_create(bus_get_dma_tag(dev), 4, PAGE_SIZE,
BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
DMA_BUFFER_SIZE, 1, DMA_BUFFER_SIZE,
0, NULL, NULL, &sc->dma_buffer_dma_tag);
bus_dmamap_create(sc->desc_dma_tag, 0,
&sc->desc_dma_map);
bus_dmamap_create(sc->dma_buffer_dma_tag, 0,
&sc->dma_buffer_dma_map);
bus_dmamem_alloc(sc->desc_dma_tag,
(void **)&sc->desc, BUS_DMA_WAITOK,
&sc->desc_dma_map);
bus_dmamem_alloc(sc->dma_buffer_dma_tag,
(void **)&sc->dma_buffer, BUS_DMA_WAITOK,
&sc->dma_buffer_dma_map);
bus_dmamap_load(sc->desc_dma_tag,
sc->desc_dma_map, sc->desc, DESC_SIZE,
ismt_single_map, &sc->desc_bus_addr, 0);
bus_dmamap_load(sc->dma_buffer_dma_tag,
sc->dma_buffer_dma_map, sc->dma_buffer, DMA_BUFFER_SIZE,
ismt_single_map, &sc->dma_buffer_bus_addr, 0);
bus_write_4(sc->mmio_res, ISMT_MSTR_MDBA,
(sc->desc_bus_addr & 0xFFFFFFFFLL));
bus_write_4(sc->mmio_res, ISMT_MSTR_MDBA + 4,
(sc->desc_bus_addr >> 32));
/* initialize the Master Control Register (MCTRL) */
bus_write_4(sc->mmio_res, ISMT_MSTR_MCTRL, ISMT_MCTRL_MEIE);
/* initialize the Master Status Register (MSTS) */
bus_write_4(sc->mmio_res, ISMT_MSTR_MSTS, 0);
/* initialize the Master Descriptor Size (MDS) */
val = bus_read_4(sc->mmio_res, ISMT_MSTR_MDS);
val &= ~ISMT_MDS_MASK;
val |= (ISMT_DESC_ENTRIES - 1);
bus_write_4(sc->mmio_res, ISMT_MSTR_MDS, val);
sc->using_msi = 1;
if (pci_msi_count(dev) == 0) {
sc->using_msi = 0;
goto intx;
}
num_vectors = 1;
if (pci_alloc_msi(dev, &num_vectors) != 0) {
sc->using_msi = 0;
goto intx;
}
sc->intr_rid = 1;
sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
&sc->intr_rid, RF_ACTIVE);
if (sc->intr_res == NULL) {
sc->using_msi = 0;
pci_release_msi(dev);
}
intx:
if (sc->using_msi == 0) {
sc->intr_rid = 0;
sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
&sc->intr_rid, RF_SHAREABLE | RF_ACTIVE);
if (sc->intr_res == NULL) {
device_printf(dev, "cannot allocate irq\n");
err = ENXIO;
goto fail;
}
}
ISMT_DEBUG(dev, "using_msi = %d\n", sc->using_msi);
err = bus_setup_intr(dev, sc->intr_res,
INTR_TYPE_MISC | INTR_MPSAFE, NULL, ismt_intr, sc,
&sc->intr_handle);
if (err != 0) {
device_printf(dev, "cannot setup interrupt\n");
err = ENXIO;
goto fail;
}
return (0);
fail:
ismt_detach(dev);
return (err);
}
static int
vga_pci_msi_count(device_t dev, device_t child)
{
return (pci_msi_count(dev));
}
/*
* Interrupt handler allocation utility. This function calls each allocation
* function as specified by arguments.
* Currently callee functions are pci_intx_alloc(), pci_msi_alloc_exact(),
* and pci_msix_alloc_exact().
* pa : pci_attach_args
* ihps : interrupt handlers
* counts : The array of number of required interrupt handlers.
* It is overwritten by allocated the number of handlers.
* CAUTION: The size of counts[] must be PCI_INTR_TYPE_SIZE.
* max_type : "max" type of using interrupts. See below.
* e.g.
* If you want to use 5 MSI-X, 1 MSI, or INTx, you use "counts" as
* int counts[PCI_INTR_TYPE_SIZE];
* counts[PCI_INTR_TYPE_MSIX] = 5;
* counts[PCI_INTR_TYPE_MSI] = 1;
* counts[PCI_INTR_TYPE_INTX] = 1;
* error = pci_intr_alloc(pa, ihps, counts, PCI_INTR_TYPE_MSIX);
*
* If you want to use hardware max number MSI-X or 1 MSI,
* and not to use INTx, you use "counts" as
* int counts[PCI_INTR_TYPE_SIZE];
* counts[PCI_INTR_TYPE_MSIX] = -1;
* counts[PCI_INTR_TYPE_MSI] = 1;
* counts[PCI_INTR_TYPE_INTX] = 0;
* error = pci_intr_alloc(pa, ihps, counts, PCI_INTR_TYPE_MSIX);
*
* If you want to use 3 MSI or INTx, you can use "counts" as
* int counts[PCI_INTR_TYPE_SIZE];
* counts[PCI_INTR_TYPE_MSI] = 3;
* counts[PCI_INTR_TYPE_INTX] = 1;
* error = pci_intr_alloc(pa, ihps, counts, PCI_INTR_TYPE_MSI);
*
* If you want to use 1 MSI or INTx (probably most general usage),
* you can simply use this API like
* below
* error = pci_intr_alloc(pa, ihps, NULL, 0);
* ^ ignored
*/
int
pci_intr_alloc(const struct pci_attach_args *pa, pci_intr_handle_t **ihps,
int *counts, pci_intr_type_t max_type)
{
int error;
int intx_count, msi_count, msix_count;
intx_count = msi_count = msix_count = 0;
if (counts == NULL) { /* simple pattern */
msi_count = 1;
intx_count = 1;
} else {
switch(max_type) {
case PCI_INTR_TYPE_MSIX:
msix_count = counts[PCI_INTR_TYPE_MSIX];
/* FALLTHROUGH */
case PCI_INTR_TYPE_MSI:
msi_count = counts[PCI_INTR_TYPE_MSI];
/* FALLTHROUGH */
case PCI_INTR_TYPE_INTX:
intx_count = counts[PCI_INTR_TYPE_INTX];
break;
default:
return EINVAL;
}
}
if (counts != NULL)
memset(counts, 0, sizeof(counts[0]) * PCI_INTR_TYPE_SIZE);
error = EINVAL;
/* try MSI-X */
if (msix_count == -1) /* use hardware max */
msix_count = pci_msix_count(pa->pa_pc, pa->pa_tag);
if (msix_count > 0) {
error = pci_msix_alloc_exact(pa, ihps, msix_count);
if (error == 0) {
KASSERTMSG(counts != NULL,
"If MSI-X is used, counts must not be NULL.");
counts[PCI_INTR_TYPE_MSIX] = msix_count;
goto out;
}
}
/* try MSI */
if (msi_count == -1) /* use hardware max */
msi_count = pci_msi_count(pa->pa_pc, pa->pa_tag);
if (msi_count > 0) {
error = pci_msi_alloc_exact(pa, ihps, msi_count);
if (error == 0) {
if (counts != NULL)
counts[PCI_INTR_TYPE_MSI] = msi_count;
goto out;
}
}
/* try INTx */
if (intx_count != 0) { /* The number of INTx is always 1. */
error = pci_intx_alloc(pa, ihps);
if (error == 0) {
if (counts != NULL)
counts[PCI_INTR_TYPE_INTX] = 1;
}
}
out:
return error;
}
static int
xhci_pci_attach(device_t self)
{
struct xhci_softc *sc = device_get_softc(self);
int count, err, rid;
/* XXX check for 64-bit capability */
if (xhci_init(sc, self)) {
device_printf(self, "Could not initialize softc\n");
goto error;
}
pci_enable_busmaster(self);
rid = PCI_XHCI_CBMEM;
sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (!sc->sc_io_res) {
device_printf(self, "Could not map memory\n");
goto error;
}
sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
sc->sc_io_size = rman_get_size(sc->sc_io_res);
usb_callout_init_mtx(&sc->sc_callout, &sc->sc_bus.bus_mtx, 0);
sc->sc_irq_rid = 0;
if (xhci_use_msi) {
count = pci_msi_count(self);
if (count >= 1) {
count = 1;
if (pci_alloc_msi(self, &count) == 0) {
if (bootverbose)
device_printf(self, "MSI enabled\n");
sc->sc_irq_rid = 1;
}
}
}
sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ,
&sc->sc_irq_rid, RF_SHAREABLE | RF_ACTIVE);
if (sc->sc_irq_res == NULL) {
device_printf(self, "Could not allocate IRQ\n");
/* goto error; FALLTHROUGH - use polling */
}
sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
if (sc->sc_bus.bdev == NULL) {
device_printf(self, "Could not add USB device\n");
goto error;
}
device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
sprintf(sc->sc_vendor, "0x%04x", pci_get_vendor(self));
if (sc->sc_irq_res != NULL) {
err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl);
if (err != 0) {
device_printf(self, "Could not setup IRQ, err=%d\n", err);
sc->sc_intr_hdl = NULL;
}
}
if (sc->sc_irq_res == NULL || sc->sc_intr_hdl == NULL ||
xhci_use_polling() != 0) {
device_printf(self, "Interrupt polling at %dHz\n", hz);
USB_BUS_LOCK(&sc->sc_bus);
xhci_interrupt_poll(sc);
USB_BUS_UNLOCK(&sc->sc_bus);
}
/* On Intel chipsets reroute ports from EHCI to XHCI controller. */
switch (pci_get_devid(self)) {
case 0x9c318086: /* Panther Point */
case 0x1e318086: /* Panther Point */
case 0x8c318086: /* Lynx Point */
sc->sc_port_route = &xhci_pci_port_route;
sc->sc_imod_default = XHCI_IMOD_DEFAULT_LP;
break;
default:
break;
}
xhci_pci_take_controller(self);
err = xhci_halt_controller(sc);
if (err == 0)
err = xhci_start_controller(sc);
if (err == 0)
err = device_probe_and_attach(sc->sc_bus.bdev);
if (err) {
device_printf(self, "XHCI halt/start/probe failed err=%d\n", err);
goto error;
}
return (0);
error:
xhci_pci_detach(self);
return (ENXIO);
}
static int
athp_pci_attach(device_t dev)
{
struct ath10k_pci *ar_pci = device_get_softc(dev);
struct ath10k *ar = &ar_pci->sc_sc;
int rid, i;
int err = 0;
int ret;
ar->sc_dev = dev;
ar->sc_invalid = 1;
/* XXX TODO: initialize sc_debug from TUNABLE */
#if 0
ar->sc_debug = ATH10K_DBG_BOOT | ATH10K_DBG_PCI | ATH10K_DBG_HTC |
ATH10K_DBG_PCI_DUMP | ATH10K_DBG_WMI | ATH10K_DBG_BMI | ATH10K_DBG_MAC |
ATH10K_DBG_WMI_PRINT | ATH10K_DBG_MGMT | ATH10K_DBG_DATA | ATH10K_DBG_HTT;
#endif
ar->sc_psc = ar_pci;
/* Load-time tunable/sysctl tree */
athp_attach_sysctl(ar);
/* Enable WMI/HTT RX for now */
ar->sc_rx_wmi = 1;
ar->sc_rx_htt = 1;
/* Fetch pcie capability offset */
ret = pci_find_cap(dev, PCIY_EXPRESS, &ar_pci->sc_cap_off);
if (ret != 0) {
device_printf(dev,
"%s: failed to find pci-express capability offset\n",
__func__);
return (ret);
}
/*
* Initialise ath10k core bits.
*/
if (ath10k_core_init(ar) < 0)
goto bad0;
/*
* Initialise ath10k freebsd bits.
*/
sprintf(ar->sc_mtx_buf, "%s:def", device_get_nameunit(dev));
mtx_init(&ar->sc_mtx, ar->sc_mtx_buf, MTX_NETWORK_LOCK,
MTX_DEF);
sprintf(ar->sc_buf_mtx_buf, "%s:buf", device_get_nameunit(dev));
mtx_init(&ar->sc_buf_mtx, ar->sc_buf_mtx_buf, "athp buf", MTX_DEF);
sprintf(ar->sc_dma_mtx_buf, "%s:dma", device_get_nameunit(dev));
mtx_init(&ar->sc_dma_mtx, ar->sc_dma_mtx_buf, "athp dma", MTX_DEF);
sprintf(ar->sc_conf_mtx_buf, "%s:conf", device_get_nameunit(dev));
mtx_init(&ar->sc_conf_mtx, ar->sc_conf_mtx_buf, "athp conf",
MTX_DEF | MTX_RECURSE);
sprintf(ar_pci->ps_mtx_buf, "%s:ps", device_get_nameunit(dev));
mtx_init(&ar_pci->ps_mtx, ar_pci->ps_mtx_buf, "athp ps", MTX_DEF);
sprintf(ar_pci->ce_mtx_buf, "%s:ce", device_get_nameunit(dev));
mtx_init(&ar_pci->ce_mtx, ar_pci->ce_mtx_buf, "athp ce", MTX_DEF);
sprintf(ar->sc_data_mtx_buf, "%s:data", device_get_nameunit(dev));
mtx_init(&ar->sc_data_mtx, ar->sc_data_mtx_buf, "athp data",
MTX_DEF);
/*
* Initialise ath10k BMI/PCIDIAG bits.
*/
ret = athp_descdma_alloc(ar, &ar_pci->sc_bmi_txbuf, "bmi_msg_req",
4, 1024);
ret |= athp_descdma_alloc(ar, &ar_pci->sc_bmi_rxbuf, "bmi_msg_resp",
4, 1024);
if (ret != 0) {
device_printf(dev, "%s: failed to allocate BMI TX/RX buffer\n",
__func__);
goto bad0;
}
/*
* Initialise HTT descriptors/memory.
*/
ret = ath10k_htt_rx_alloc_desc(ar, &ar->htt);
if (ret != 0) {
device_printf(dev, "%s: failed to alloc HTT RX descriptors\n",
__func__);
goto bad;
}
/* XXX here instead of in core_init because we need the lock init'ed */
callout_init_mtx(&ar->scan.timeout, &ar->sc_data_mtx, 0);
ar_pci->pipe_taskq = taskqueue_create("athp pipe taskq", M_NOWAIT,
NULL, ar_pci);
(void) taskqueue_start_threads(&ar_pci->pipe_taskq, 1, PI_NET, "%s pipe taskq",
device_get_nameunit(dev));
if (ar_pci->pipe_taskq == NULL) {
device_printf(dev, "%s: couldn't create pipe taskq\n",
__func__);
err = ENXIO;
goto bad;
}
/*
* Look at the device/vendor ID and choose which register offset
* mapping to use. This is used by a lot of the register access
* pieces to get the correct device-specific windows.
*/
ar_pci->sc_vendorid = pci_get_vendor(dev);
ar_pci->sc_deviceid = pci_get_device(dev);
if (athp_pci_hw_lookup(ar_pci) != 0) {
device_printf(dev, "%s: hw lookup failed\n", __func__);
err = ENXIO;
goto bad;
}
/*
* Enable bus mastering.
*/
pci_enable_busmaster(dev);
/*
* Setup memory-mapping of PCI registers.
*/
rid = BS_BAR;
ar_pci->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (ar_pci->sc_sr == NULL) {
device_printf(dev, "cannot map register space\n");
err = ENXIO;
goto bad;
}
/* Driver copy; hopefully we can delete this */
ar->sc_st = rman_get_bustag(ar_pci->sc_sr);
ar->sc_sh = rman_get_bushandle(ar_pci->sc_sr);
/* Local copy for bus operations */
ar_pci->sc_st = rman_get_bustag(ar_pci->sc_sr);
ar_pci->sc_sh = rman_get_bushandle(ar_pci->sc_sr);
/*
* Mark device invalid so any interrupts (shared or otherwise)
* that arrive before the HAL is setup are discarded.
*/
ar->sc_invalid = 1;
printf("%s: msicount=%d, msixcount=%d\n",
__func__,
pci_msi_count(dev),
pci_msix_count(dev));
/*
* Arrange interrupt line.
*
* XXX TODO: this is effictively ath10k_pci_init_irq().
* Refactor it out later.
*
* First - attempt MSI. If we get it, then use it.
*/
i = MSI_NUM_REQUEST;
if (pci_alloc_msi(dev, &i) == 0) {
device_printf(dev, "%s: %d MSI interrupts\n", __func__, i);
ar_pci->num_msi_intrs = MSI_NUM_REQUEST;
} else {
i = 1;
if (pci_alloc_msi(dev, &i) == 0) {
device_printf(dev, "%s: 1 MSI interrupt\n", __func__);
ar_pci->num_msi_intrs = 1;
} else {
device_printf(dev, "%s: legacy interrupts\n", __func__);
ar_pci->num_msi_intrs = 0;
}
}
err = ath10k_pci_request_irq(ar_pci);
if (err != 0)
goto bad1;
/*
* Attach register ops - needed for the caller to do register IO.
*/
ar->sc_regio.reg_read = athp_pci_regio_read_reg;
ar->sc_regio.reg_write = athp_pci_regio_write_reg;
ar->sc_regio.reg_s_read = athp_pci_regio_s_read_reg;
ar->sc_regio.reg_s_write = athp_pci_regio_s_write_reg;
ar->sc_regio.reg_flush = athp_pci_regio_flush_reg;
ar->sc_regio.reg_arg = ar_pci;
/*
* TODO: abstract this out to be a bus/hif specific
* attach path.
*
* I'm not sure what USB/SDIO will look like here, but
* I'm pretty sure it won't involve PCI/CE setup.
* It'll still have WME/HIF/BMI, but it'll be done over
* USB endpoints.
*/
if (athp_pci_setup_bufs(ar_pci) != 0) {
err = ENXIO;
goto bad4;
}
/* HIF ops attach */
ar->hif.ops = &ath10k_pci_hif_ops;
ar->hif.bus = ATH10K_BUS_PCI;
/* Alloc pipes */
ret = ath10k_pci_alloc_pipes(ar);
if (ret) {
device_printf(ar->sc_dev, "%s: pci_alloc_pipes failed: %d\n",
__func__,
ret);
/* XXX cleanup */
err = ENXIO;
goto bad4;
}
/* deinit ce */
ath10k_pci_ce_deinit(ar);
/* disable irq */
ret = ath10k_pci_irq_disable(ar_pci);
if (ret) {
device_printf(ar->sc_dev, "%s: irq_disable failed: %d\n",
__func__,
ret);
err = ENXIO;
goto bad4;
}
/* init IRQ */
ret = ath10k_pci_init_irq(ar_pci);
if (ret) {
device_printf(ar->sc_dev, "%s: init_irq failed: %d\n",
__func__,
ret);
err = ENXIO;
goto bad4;
}
/* Ok, gate open the interrupt handler */
ar->sc_invalid = 0;
/* pci_chip_reset */
ret = ath10k_pci_chip_reset(ar_pci);
if (ret) {
device_printf(ar->sc_dev, "%s: chip_reset failed: %d\n",
__func__,
ret);
err = ENXIO;
goto bad4;
}
/* read SoC/chip version */
ar->sc_chipid = athp_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS(ar->sc_regofs));
/* Verify chip version is something we can use */
device_printf(ar->sc_dev, "%s: chipid: 0x%08x\n", __func__, ar->sc_chipid);
if (! ath10k_pci_chip_is_supported(ar_pci->sc_deviceid, ar->sc_chipid)) {
device_printf(ar->sc_dev,
"%s: unsupported chip; chipid: 0x%08x\n", __func__,
ar->sc_chipid);
err = ENXIO;
goto bad4;
}
/* Call main attach method with given info */
ar->sc_preinit_hook.ich_func = athp_attach_preinit;
ar->sc_preinit_hook.ich_arg = ar;
if (config_intrhook_establish(&ar->sc_preinit_hook) != 0) {
device_printf(ar->sc_dev,
"%s: couldn't establish preinit hook\n", __func__);
goto bad4;
}
return (0);
/* Fallthrough for setup failure */
bad4:
athp_pci_free_bufs(ar_pci);
/* Ensure we disable interrupts from the device */
ath10k_pci_deinit_irq(ar_pci);
ath10k_pci_free_irq(ar_pci);
bad1:
bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, ar_pci->sc_sr);
bad:
ath10k_htt_rx_free_desc(ar, &ar->htt);
athp_descdma_free(ar, &ar_pci->sc_bmi_txbuf);
athp_descdma_free(ar, &ar_pci->sc_bmi_rxbuf);
/* XXX disable busmaster? */
mtx_destroy(&ar_pci->ps_mtx);
mtx_destroy(&ar_pci->ce_mtx);
mtx_destroy(&ar->sc_conf_mtx);
mtx_destroy(&ar->sc_data_mtx);
mtx_destroy(&ar->sc_buf_mtx);
mtx_destroy(&ar->sc_dma_mtx);
mtx_destroy(&ar->sc_mtx);
if (ar_pci->pipe_taskq) {
taskqueue_drain_all(ar_pci->pipe_taskq);
taskqueue_free(ar_pci->pipe_taskq);
}
/* Shutdown ioctl handler */
athp_ioctl_teardown(ar);
ath10k_core_destroy(ar);
bad0:
return (err);
}
static int
xhci_pci_attach(device_t self)
{
struct xhci_softc *sc = device_get_softc(self);
int count, err, rid;
uint8_t usedma32;
rid = PCI_XHCI_CBMEM;
sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (!sc->sc_io_res) {
device_printf(self, "Could not map memory\n");
return (ENOMEM);
}
sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
sc->sc_io_size = rman_get_size(sc->sc_io_res);
/* check for USB 3.0 controllers which don't support 64-bit DMA */
switch (pci_get_devid(self)) {
case 0x01941033: /* NEC uPD720200 USB 3.0 controller */
case 0x00141912: /* NEC uPD720201 USB 3.0 controller */
case 0x78141022: /* AMD A10-7300, tested does not work w/64-bit DMA */
usedma32 = 1;
break;
default:
usedma32 = 0;
break;
}
if (xhci_init(sc, self, usedma32)) {
device_printf(self, "Could not initialize softc\n");
bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM,
sc->sc_io_res);
return (ENXIO);
}
pci_enable_busmaster(self);
usb_callout_init_mtx(&sc->sc_callout, &sc->sc_bus.bus_lock, 0);
rid = 0;
if (xhci_use_msi) {
count = pci_msi_count(self);
if (count >= 1) {
count = 1;
if (pci_alloc_msi(self, &rid, 1, count) == 0) {
if (bootverbose)
device_printf(self, "MSI enabled\n");
sc->sc_irq_rid = 1;
}
}
}
/*
* hw.usb.xhci.use_polling=1 to force polling.
*/
if (xhci_use_polling() == 0) {
sc->sc_irq_res = bus_alloc_resource_any(
self, SYS_RES_IRQ,
&sc->sc_irq_rid,
RF_SHAREABLE | RF_ACTIVE);
if (sc->sc_irq_res == NULL) {
pci_release_msi(self);
device_printf(self, "Could not allocate IRQ\n");
/* goto error; FALLTHROUGH - use polling */
}
}
sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
if (sc->sc_bus.bdev == NULL) {
device_printf(self, "Could not add USB device\n");
goto error;
}
device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
ksprintf(sc->sc_vendor, "0x%04x", pci_get_vendor(self));
if (sc->sc_irq_res != NULL) {
err = bus_setup_intr(self, sc->sc_irq_res, INTR_MPSAFE,
(driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl, NULL);
if (err != 0) {
bus_release_resource(self, SYS_RES_IRQ,
rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
sc->sc_irq_res = NULL;
pci_release_msi(self);
device_printf(self, "Could not setup IRQ, err=%d\n", err);
sc->sc_intr_hdl = NULL;
}
}
if (sc->sc_irq_res == NULL || sc->sc_intr_hdl == NULL) {
if (xhci_use_polling() != 0) {
device_printf(self, "Interrupt polling at %dHz\n", hz);
USB_BUS_LOCK(&sc->sc_bus);
xhci_interrupt_poll(sc);
USB_BUS_UNLOCK(&sc->sc_bus);
} else
goto error;
}
/* On Intel chipsets reroute ports from EHCI to XHCI controller. */
switch (pci_get_devid(self)) {
case 0x0f358086: /* BayTrail */
case 0x9c318086: /* Panther Point */
case 0x1e318086: /* Panther Point */
case 0x8c318086: /* Lynx Point */
case 0x8cb18086: /* Wildcat Point */
case 0x9cb18086: /* Wildcat Point-LP */
sc->sc_port_route = &xhci_pci_port_route;
sc->sc_imod_default = XHCI_IMOD_DEFAULT_LP;
break;
default:
break;
}
xhci_pci_take_controller(self);
err = xhci_halt_controller(sc);
if (err == 0)
err = xhci_start_controller(sc);
if (err == 0)
err = device_probe_and_attach(sc->sc_bus.bdev);
if (err) {
device_printf(self, "XHCI halt/start/probe failed err=%d\n", err);
goto error;
}
return (0);
error:
xhci_pci_detach(self);
return (ENXIO);
}
