PRIVATE void pci_scan_devices(int bus_nr)
{
printl("PCI: Scanning PCI devices...\n");
int i = 0, func = 0;
for(i = 0; i < 32; i++)
{
for (func = 0; func < 8; func++) {
u16 vendor = pci_read_word(bus_nr, i, func, 0);
u16 device = pci_read_word(bus_nr, i, func, 2);
if(vendor == 0xFFFF)
continue;
char * name = pci_dev_name(vendor, device);
if (name) {
printl("PCI: %d.%02x.%x: (0x%04x:0x%04x) %s\n", bus_nr, i, func, vendor, device, name);
} else {
printl("PCI: %d.%02x.%x: Unknown device (0x%04x:0x%04x)\n", bus_nr, i, func, vendor, device);
}
}
}
return;
}
uint16_t pciCheckVendor(uint16_t bus, uint16_t slot)
{
uint16_t vendor,device;
/* check if device is valid */
if ((vendor = pci_read_word(bus,slot,0,0)) != 0xFFFF) {
device = pci_read_word(bus,slot,0,2);
/* valid device */
} return (vendor);
}
static void
exec_op(struct op *op, struct pci_dev *dev)
{
char *mm[] = { NULL, "%02x", "%04x", NULL, "%08x" };
char *m = mm[op->width];
unsigned int x;
int i, addr;
if (verbose)
printf("%02x:%02x.%x:%02x", dev->bus, dev->dev, dev->func, op->addr);
addr = op->addr;
if (op->num_values >= 0)
for(i=0; i<op->num_values; i++)
{
if (verbose)
{
putchar(' ');
printf(m, op->values[i]);
}
if (demo_mode)
continue;
switch (op->width)
{
case 1:
pci_write_byte(dev, addr, op->values[i]);
break;
case 2:
pci_write_word(dev, addr, op->values[i]);
break;
default:
pci_write_long(dev, addr, op->values[i]);
break;
}
addr += op->width;
}
else
{
if (verbose)
printf(" = ");
if (!demo_mode)
{
switch (op->width)
{
case 1:
x = pci_read_byte(dev, addr);
break;
case 2:
x = pci_read_word(dev, addr);
break;
default:
x = pci_read_long(dev, addr);
break;
}
printf(m, x);
}
else
putchar('?');
}
putchar('\n');
}
static int board_via_epia_m(const char *name)
{
struct pci_dev *dev;
unsigned int base;
uint8_t val;
dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */
if (!dev) {
fprintf(stderr, "\nERROR: VT8235 ISA Bridge not found.\n");
return -1;
}
/* GPIO12-15 -> output */
val = pci_read_byte(dev, 0xE4);
val |= 0x10;
pci_write_byte(dev, 0xE4, val);
/* Get Power Management IO address. */
base = pci_read_word(dev, 0x88) & 0xFF80;
/* enable GPIO15 which is connected to write protect. */
val = inb(base + 0x4D);
val |= 0x80;
outb(val, base + 0x4D);
return 0;
}
static int get_bit_gpio(llio_t *self) {
board_t *board = self->board;
u16 data;
data = pci_read_word(board->dev, XIO2001_GPIO_DATA_REG);
if (data & 0x4)
return 1;
else
return 0;
}
struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device,
uint16_t card_vendor, uint16_t card_device)
{
struct pci_dev *temp;
struct pci_filter filter;
pci_filter_init(NULL, &filter);
filter.vendor = vendor;
filter.device = device;
for (temp = pacc->devices; temp; temp = temp->next)
if (pci_filter_match(&filter, temp)) {
if ((card_vendor ==
pci_read_word(temp, PCI_SUBSYSTEM_VENDOR_ID))
&& (card_device ==
pci_read_word(temp, PCI_SUBSYSTEM_ID)))
return temp;
}
return NULL;
}
struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t devclass)
{
struct pci_dev *temp;
struct pci_filter filter;
uint16_t tmp2;
pci_filter_init(NULL, &filter);
filter.vendor = vendor;
for (temp = pacc->devices; temp; temp = temp->next)
if (pci_filter_match(&filter, temp)) {
/* Read PCI class */
tmp2 = pci_read_word(temp, 0x0a);
if (tmp2 == devclass)
return temp;
}
return NULL;
}
static void
perform_reads(struct pci_dev * dev,
unsigned long * timestamps,
uint64_t iteration_count,
uint64_t wait_time_us)
{
size_t i;
for (i = 0; i != iteration_count; ++i)
{
struct timestamp t;
read_timestamp_counter(&t);
pci_read_word(dev, PCI_VENDOR_ID);
timestamps[i] = cycle_since_timestamp(&t);
if (wait_time_us)
usleep(wait_time_us);
}
}
static void process_uhci(struct pci_address* addr, pci_device* dev)
{
uint8_t revision = pci_read_byte(addr, 0x60);
if(revision != UHCI_REV_1_0) {
// This host controller indicates that it supports a version
// of the USB specification that is *not* 1.0. Ignore it
KWARN("Detected UHCI with unsupported revision, ignoring...");
return;
}
// Bit 0 indicates whether it's memory mapped or port I/O
bool memory_mapped = (dev->base_addr4 & 0x1) == 1;
// Beore we initialize the card, make sure the cards I/O is disabled
uint16_t cmd = pci_read_word(addr, PCI_COMMAND_REG_OFFSET);
cmd = (cmd & ~0x1);
pci_write_word(addr, PCI_COMMAND_REG_OFFSET, cmd);
// THe USB book I'm reading is telling me to null out the
// capabilities register as well as the two registers marked as "reserved"
// Not sure why, TODO: Investigate! :-S
pci_write_dword(addr, PCI_CAPS_OFF_REG_OFFSET, 0x00000000);
pci_write_dword(addr, 0x38, 0x00000000);
// Set the IRQ
pci_write_byte(addr, PCI_IRQ_REG_OFFSET, UHCI_IRQ);
// Now try to get the size of the address space
//uint32_t size = pci_device_get_memory_size(addr, PCI_BASE_ADDR4_REG_OFFSET);
// Enable bus mastering and I/O access
pci_write_word(addr, 0x04, memory_mapped ? 0x06 : 0x05);
// Disable legacy support and clear current status
pci_write_word(addr, PCI_LEG_SUP_REG_OFFSET,
PCI_LEGACY_PTS | // Clear Sequence ended bit
PCI_LEGACY_TBY64W | PCI_LEGACY_TBY64R | PCI_LEGACY_TBY60W | PCI_LEGACY_TBY60R); // Clear status
// The device is now ready for the UHCI driver to take over
uhci_init(dev->base_addr4, dev, addr, UHCI_IRQ);
}
int show_pci(void)
{
struct pci_access *pacc;
struct pci_dev *dev;
unsigned int c;
pacc = pci_alloc(); /* Get the pci_access structure */
/* Set all options you want -- here we stick with the defaults */
pacc->debugging=1;
pci_init(pacc); /* Initialize the PCI library */
pci_scan_bus(pacc); /* We want to get the list of devices */
for(dev=pacc->devices; dev; dev=dev->next) /* Iterate over all devices */
{
pci_fill_info(dev, PCI_FILL_IDENT | PCI_FILL_BASES); /* Fill in header info we need */
c = pci_read_word(dev, PCI_CLASS_DEVICE); /* Read config register directly */
printf("%02x:%02x.%d vendor=%04x device=%04x class=%04x irq=%d base0=%lx\n",
dev->bus, dev->dev, dev->func, dev->vendor_id, dev->device_id,
c, dev->irq, dev->base_addr[0]);
}
pci_cleanup(pacc); /* Close everything */
return 0;
}
int do_post(void)
{
struct pci_dev *p;
unsigned int c;
unsigned int pci_id;
int error;
pci_scan_bus(pacc);
for (p = pacc->devices; p; p = p->next) {
c = pci_read_word(p, PCI_CLASS_DEVICE);
if (c == 0x300) {
pci_id =
(p->bus << 8) + (p->dev << 3) +
(p->func & 0x7);
error = do_real_post(pci_id);
if (error != 0) {
return error;
}
}
}
return 0;
}
bool pci_device_get_next(struct pci_address* addr, int16_t class_id, int16_t sub_class, pci_device* result)
{
uint32_t* res_device_ptr = (uint32_t*)(result);
for(; addr->bus < MAX_PCI_BUS_NR; addr->bus++)
{
for(; addr->device < MAX_PCI_BUS_DEV_NR; addr->device++)
{
for(; addr->func < MAX_FUNC_PER_PCI_BUS_DEV; addr->func++)
{
if(pci_read_word(addr, PCI_VENDOR_ID_REG_OFFSET) == PCI_VENDOR_ID_NO_DEVICE)
continue;
if(class_id != -1 && pci_read_byte(addr, PCI_DEV_CLASS_REG_OFFSET) != class_id)
continue;
if(sub_class != -1 && pci_read_byte(addr, PCI_DEV_SUB_CLASS_REG_OFFSET) != sub_class)
continue;
// Device found, read in the entire configuration space
for (uint8_t i = 0; i < 64; i++)
res_device_ptr[i] = pci_read_dword(addr, (i << 2));
return true;
}
// Ensure we scan all functions on the next device
addr->func = 0;
}
// Ensure we scan all devices on the next bus
addr->device = 0;
}
return false; // No more devices
}
uint16_t detect_ec(void)
{
uint16_t ec_port;
struct pci_dev *dev;
dev = pci_dev_find(0x1002, 0x439d);
if (!dev) {
return 0;
}
/* is EC disabled ? */
if (!(pci_read_byte(dev, 0x40) & (1 << 7)))
return 0;
ec_port = pci_read_word(dev, 0xa4);
if (!(ec_port & 0x1))
return 0;
ec_port &= ~0x1;
return ec_port;
}
static void
pci_scan_trad_caps(struct pci_dev *d)
{
word status = pci_read_word(d, PCI_STATUS);
byte been_there[256];
int where;
if (!(status & PCI_STATUS_CAP_LIST))
return;
memset(been_there, 0, 256);
where = pci_read_byte(d, PCI_CAPABILITY_LIST) & ~3;
while (where)
{
byte id = pci_read_byte(d, where + PCI_CAP_LIST_ID);
byte next = pci_read_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
if (been_there[where]++)
break;
if (id == 0xff)
break;
pci_add_cap(d, where, id, PCI_CAP_NORMAL);
where = next;
}
}
uintptr_t pcidev_readbar(struct pci_dev *dev, int bar)
{
uint64_t addr;
uint32_t upperaddr;
uint8_t headertype;
uint16_t supported_cycles;
enum pci_bartype bartype = TYPE_UNKNOWN;
headertype = pci_read_byte(dev, PCI_HEADER_TYPE) & 0x7f;
msg_pspew("PCI header type 0x%02x\n", headertype);
/* Don't use dev->base_addr[x] (as value for 'bar'), won't work on older libpci. */
addr = pci_read_long(dev, bar);
/* Sanity checks. */
switch (headertype) {
case PCI_HEADER_TYPE_NORMAL:
switch (bar) {
case PCI_BASE_ADDRESS_0:
case PCI_BASE_ADDRESS_1:
case PCI_BASE_ADDRESS_2:
case PCI_BASE_ADDRESS_3:
case PCI_BASE_ADDRESS_4:
case PCI_BASE_ADDRESS_5:
if ((addr & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO)
bartype = TYPE_IOBAR;
else
bartype = TYPE_MEMBAR;
break;
case PCI_ROM_ADDRESS:
bartype = TYPE_ROMBAR;
break;
}
break;
case PCI_HEADER_TYPE_BRIDGE:
switch (bar) {
case PCI_BASE_ADDRESS_0:
case PCI_BASE_ADDRESS_1:
if ((addr & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO)
bartype = TYPE_IOBAR;
else
bartype = TYPE_MEMBAR;
break;
case PCI_ROM_ADDRESS1:
bartype = TYPE_ROMBAR;
break;
}
break;
case PCI_HEADER_TYPE_CARDBUS:
break;
default:
msg_perr("Unknown PCI header type 0x%02x, BAR type cannot be determined reliably.\n",
headertype);
break;
}
supported_cycles = pci_read_word(dev, PCI_COMMAND);
msg_pdbg("Requested BAR is of type ");
switch (bartype) {
case TYPE_MEMBAR:
msg_pdbg("MEM");
if (!(supported_cycles & PCI_COMMAND_MEMORY)) {
msg_perr("MEM BAR access requested, but device has MEM space accesses disabled.\n");
/* TODO: Abort here? */
}
msg_pdbg(", %sbit, %sprefetchable\n",
((addr & 0x6) == 0x0) ? "32" : (((addr & 0x6) == 0x4) ? "64" : "reserved"),
(addr & 0x8) ? "" : "not ");
if ((addr & 0x6) == 0x4) {
/* The spec says that a 64-bit register consumes
* two subsequent dword locations.
*/
upperaddr = pci_read_long(dev, bar + 4);
if (upperaddr != 0x00000000) {
/* Fun! A real 64-bit resource. */
if (sizeof(uintptr_t) != sizeof(uint64_t)) {
msg_perr("BAR unreachable!");
/* TODO: Really abort here? If multiple PCI devices match,
* we might never tell the user about the other devices.
*/
return 0;
}
addr |= (uint64_t)upperaddr << 32;
}
}
addr &= PCI_BASE_ADDRESS_MEM_MASK;
break;
case TYPE_IOBAR:
msg_pdbg("I/O\n");
#if __FLASHROM_HAVE_OUTB__
if (!(supported_cycles & PCI_COMMAND_IO)) {
msg_perr("I/O BAR access requested, but device has I/O space accesses disabled.\n");
/* TODO: Abort here? */
}
#else
msg_perr("I/O BAR access requested, but flashrom does not support I/O BAR access on this "
"platform (yet).\n");
#endif
addr &= PCI_BASE_ADDRESS_IO_MASK;
break;
case TYPE_ROMBAR:
msg_pdbg("ROM\n");
/* Not sure if this check is needed. */
if (!(supported_cycles & PCI_COMMAND_MEMORY)) {
msg_perr("MEM BAR access requested, but device has MEM space accesses disabled.\n");
/* TODO: Abort here? */
}
addr &= PCI_ROM_ADDRESS_MASK;
break;
case TYPE_UNKNOWN:
msg_perr("BAR type unknown, please report a bug at [email protected]\n");
}
return (uintptr_t)addr;
}
int print_gpios(struct pci_dev *sb)
{
int i, size;
uint16_t gpiobase;
const io_register_t *gpio_registers;
printf("\n============= GPIOS =============\n\n");
switch (sb->device_id) {
case PCI_DEVICE_ID_INTEL_ICH10R:
gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
gpio_registers = ich10_gpio_registers;
size = ARRAY_SIZE(ich10_gpio_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH9DH:
case PCI_DEVICE_ID_INTEL_ICH9DO:
case PCI_DEVICE_ID_INTEL_ICH9R:
case PCI_DEVICE_ID_INTEL_ICH9:
case PCI_DEVICE_ID_INTEL_ICH9M:
case PCI_DEVICE_ID_INTEL_ICH9ME:
gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
gpio_registers = ich9_gpio_registers;
size = ARRAY_SIZE(ich9_gpio_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH8:
case PCI_DEVICE_ID_INTEL_ICH8M:
gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
gpio_registers = ich8_gpio_registers;
size = ARRAY_SIZE(ich8_gpio_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH7:
case PCI_DEVICE_ID_INTEL_ICH7M:
case PCI_DEVICE_ID_INTEL_ICH7DH:
case PCI_DEVICE_ID_INTEL_ICH7MDH:
case PCI_DEVICE_ID_INTEL_NM10:
gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
gpio_registers = ich7_gpio_registers;
size = ARRAY_SIZE(ich7_gpio_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH6:
gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
gpio_registers = ich6_gpio_registers;
size = ARRAY_SIZE(ich6_gpio_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH5:
gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
gpio_registers = ich5_gpio_registers;
size = ARRAY_SIZE(ich5_gpio_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH4:
case PCI_DEVICE_ID_INTEL_ICH4M:
gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
gpio_registers = ich4_gpio_registers;
size = ARRAY_SIZE(ich4_gpio_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH2:
gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
gpio_registers = ich2_gpio_registers;
size = ARRAY_SIZE(ich2_gpio_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH:
case PCI_DEVICE_ID_INTEL_ICH0:
gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
gpio_registers = ich0_gpio_registers;
size = ARRAY_SIZE(ich0_gpio_registers);
break;
case PCI_DEVICE_ID_INTEL_82371XX:
printf("This southbridge has GPIOs in the PM unit.\n");
return 1;
case 0x1234: // Dummy for non-existent functionality
printf("This southbridge does not have GPIOBASE.\n");
return 1;
default:
printf("Error: Dumping GPIOs on this southbridge is not (yet) supported.\n");
return 1;
}
printf("GPIOBASE = 0x%04x (IO)\n\n", gpiobase);
for (i = 0; i < size; i++) {
switch (gpio_registers[i].size) {
case 4:
printf("gpiobase+0x%04x: 0x%08x (%s)\n",
gpio_registers[i].addr,
inl(gpiobase+gpio_registers[i].addr),
gpio_registers[i].name);
break;
case 2:
printf("gpiobase+0x%04x: 0x%04x (%s)\n",
gpio_registers[i].addr,
inw(gpiobase+gpio_registers[i].addr),
gpio_registers[i].name);
break;
case 1:
printf("gpiobase+0x%04x: 0x%02x (%s)\n",
gpio_registers[i].addr,
inb(gpiobase+gpio_registers[i].addr),
gpio_registers[i].name);
break;
}
}
return 0;
}
uint16_t getSubClassId(uint16_t bus, uint16_t device, uint16_t function)
{
uint32_t r0 = pci_read_word(bus,device,function,0xA);
return (r0 & ~0xFF00);
}
void pci::probe(void) {
pci_scan_bus(_pacc);
uint8_t buf[CONFIG_SPACE_SIZE] = {0};
char classbuf[128] = {0}, vendorbuf[128] {0}, devbuf[128] = {0};
for (struct pci_dev *dev = _pacc->devices; dev && _entries.size() < MAX_DEVICES; dev = dev->next) {
_entries.push_back(pciEntry());
pciEntry &e = _entries.back();
memset(buf, 0, sizeof(buf));
memset(classbuf, 0, sizeof(classbuf));
memset(vendorbuf, 0, sizeof(vendorbuf));
memset(devbuf, 0, sizeof(devbuf));
pci_setup_cache(dev, buf, CONFIG_SPACE_SIZE);
pci_read_block(dev, 0, buf, CONFIG_SPACE_SIZE);
pci_fill_info(dev, PCI_FILL_IDENT | PCI_FILL_CLASS | PCI_FILL_CAPS);
pci_lookup_name(_pacc, vendorbuf, sizeof(vendorbuf), PCI_LOOKUP_VENDOR, dev->vendor_id, dev->device_id);
pci_lookup_name(_pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, dev->vendor_id, dev->device_id);
e.text.append(vendorbuf).append("|").append(devbuf);
e.class_type += classbuf;
e.vendor = dev->vendor_id;
e.device = dev->device_id;
e.pci_domain = dev->domain;
e.bus = dev->bus;
e.pciusb_device = dev->dev;
e.pci_function = dev->func;
e.class_id = dev->device_class;
e.subvendor = pci_read_word(dev, PCI_SUBSYSTEM_VENDOR_ID);
e.subdevice = pci_read_word(dev, PCI_SUBSYSTEM_ID);
e.pci_revision = pci_read_byte(dev, PCI_REVISION_ID);
if ((e.subvendor == 0 && e.subdevice == 0) ||
(e.subvendor == e.vendor && e.subdevice == e.device)) {
e.subvendor = 0xffff;
e.subdevice = 0xffff;
}
if (pci_find_cap(dev,PCI_CAP_ID_EXP, PCI_CAP_NORMAL))
e.is_pciexpress = true;
/* special case for realtek 8139 that has two drivers */
if (e.vendor == 0x10ec && e.device == 0x8139) {
if (e.pci_revision < 0x20)
e.module = "8139too";
else
e.module = "8139cp";
}
}
// fake two PCI controllers for xen
struct stat sb;
if (!stat("/sys/bus/xen", &sb)) {
// FIXME: use C++ streams..
FILE *f;
if ((f = fopen("/sys/hypervisor/uuid", "r"))) {
char buf[38];
fgets(buf, sizeof(buf) - 1, f);
fclose(f);
if (strncmp(buf, "00000000-0000-0000-0000-000000000000", sizeof(buf))) {
// We're now sure to be in a Xen guest:
{
_entries.push_back(pciEntry());
pciEntry &e = _entries.back();
e.text.append("XenSource, Inc.|Block Frontend");
e.class_id = 0x0106; // STORAGE_SATA
e.vendor = 0x1a71; // XenSource
e.device = 0xfffa; // fake
e.subvendor = 0;
e.subdevice = 0;
e.class_id = 0x0106;
e.module = "xen_blkfront";
}
{
_entries.push_back(pciEntry());
pciEntry &e = _entries.back();
e.text.append("XenSource, Inc.|Network Frontend");
e.class_id = 0x0200; // NETWORK_ETHERNET
e.vendor = 0x1a71; // XenSource
e.device = 0xfffb; // fake
e.subvendor = 0;
e.subdevice = 0;
e.class_id = 0x0200;
e.module = "xen_netfront";
}
}
}
}
findModules("pcitable", false);
}
int print_pmbase(struct pci_dev *sb, struct pci_access *pacc)
{
int i, size;
uint16_t pmbase;
const io_register_t *pm_registers;
struct pci_dev *acpi;
printf("\n============= PMBASE ============\n\n");
switch (sb->device_id) {
case PCI_DEVICE_ID_INTEL_3400:
case PCI_DEVICE_ID_INTEL_3420:
case PCI_DEVICE_ID_INTEL_3450:
case PCI_DEVICE_ID_INTEL_3400_DESKTOP:
case PCI_DEVICE_ID_INTEL_3400_MOBILE:
case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF:
case PCI_DEVICE_ID_INTEL_B55_A:
case PCI_DEVICE_ID_INTEL_B55_B:
case PCI_DEVICE_ID_INTEL_H55:
case PCI_DEVICE_ID_INTEL_H57:
case PCI_DEVICE_ID_INTEL_HM55:
case PCI_DEVICE_ID_INTEL_HM57:
case PCI_DEVICE_ID_INTEL_P55:
case PCI_DEVICE_ID_INTEL_PM55:
case PCI_DEVICE_ID_INTEL_Q57:
case PCI_DEVICE_ID_INTEL_QM57:
case PCI_DEVICE_ID_INTEL_QS57:
case PCI_DEVICE_ID_INTEL_Z68:
case PCI_DEVICE_ID_INTEL_P67:
case PCI_DEVICE_ID_INTEL_UM67:
case PCI_DEVICE_ID_INTEL_HM65:
case PCI_DEVICE_ID_INTEL_H67:
case PCI_DEVICE_ID_INTEL_HM67:
case PCI_DEVICE_ID_INTEL_Q65:
case PCI_DEVICE_ID_INTEL_QS67:
case PCI_DEVICE_ID_INTEL_Q67:
case PCI_DEVICE_ID_INTEL_QM67:
case PCI_DEVICE_ID_INTEL_B65:
case PCI_DEVICE_ID_INTEL_C202:
case PCI_DEVICE_ID_INTEL_C204:
case PCI_DEVICE_ID_INTEL_C206:
case PCI_DEVICE_ID_INTEL_H61:
case PCI_DEVICE_ID_INTEL_Z77:
case PCI_DEVICE_ID_INTEL_Z75:
case PCI_DEVICE_ID_INTEL_Q77:
case PCI_DEVICE_ID_INTEL_Q75:
case PCI_DEVICE_ID_INTEL_B75:
case PCI_DEVICE_ID_INTEL_H77:
case PCI_DEVICE_ID_INTEL_C216:
case PCI_DEVICE_ID_INTEL_QM77:
case PCI_DEVICE_ID_INTEL_QS77:
case PCI_DEVICE_ID_INTEL_HM77:
case PCI_DEVICE_ID_INTEL_UM77:
case PCI_DEVICE_ID_INTEL_HM76:
case PCI_DEVICE_ID_INTEL_HM75:
case PCI_DEVICE_ID_INTEL_HM70:
case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL:
case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM:
case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
case PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC:
pmbase = pci_read_word(sb, 0x40) & 0xff80;
pm_registers = pch_pm_registers;
size = ARRAY_SIZE(pch_pm_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH10R:
pmbase = pci_read_word(sb, 0x40) & 0xff80;
pm_registers = ich10_pm_registers;
size = ARRAY_SIZE(ich10_pm_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH7:
case PCI_DEVICE_ID_INTEL_ICH7M:
case PCI_DEVICE_ID_INTEL_ICH7DH:
case PCI_DEVICE_ID_INTEL_ICH7MDH:
case PCI_DEVICE_ID_INTEL_NM10:
pmbase = pci_read_word(sb, 0x40) & 0xfffc;
pm_registers = ich7_pm_registers;
size = ARRAY_SIZE(ich7_pm_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH9DH:
case PCI_DEVICE_ID_INTEL_ICH9DO:
case PCI_DEVICE_ID_INTEL_ICH9R:
case PCI_DEVICE_ID_INTEL_ICH9:
case PCI_DEVICE_ID_INTEL_ICH9M:
case PCI_DEVICE_ID_INTEL_ICH9ME:
pmbase = pci_read_word(sb, 0x40) & 0xfffc;
pm_registers = ich9_pm_registers;
size = ARRAY_SIZE(ich9_pm_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH8:
case PCI_DEVICE_ID_INTEL_ICH8M:
case PCI_DEVICE_ID_INTEL_ICH8ME:
pmbase = pci_read_word(sb, 0x40) & 0xfffc;
pm_registers = ich8_pm_registers;
size = ARRAY_SIZE(ich8_pm_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH6:
pmbase = pci_read_word(sb, 0x40) & 0xfffc;
pm_registers = ich6_pm_registers;
size = ARRAY_SIZE(ich6_pm_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH5:
pmbase = pci_read_word(sb, 0x40) & 0xfffc;
pm_registers = ich5_pm_registers;
size = ARRAY_SIZE(ich5_pm_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH4:
pmbase = pci_read_word(sb, 0x40) & 0xfffc;
pm_registers = ich4_pm_registers;
size = ARRAY_SIZE(ich4_pm_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH2:
pmbase = pci_read_word(sb, 0x40) & 0xfffc;
pm_registers = ich2_pm_registers;
size = ARRAY_SIZE(ich2_pm_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH0:
pmbase = pci_read_word(sb, 0x40) & 0xfffc;
pm_registers = ich0_pm_registers;
size = ARRAY_SIZE(ich0_pm_registers);
break;
case PCI_DEVICE_ID_INTEL_82371XX:
acpi = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 3);
if (!acpi) {
printf("Southbridge function 3 not found.\n");
return 1;
}
pmbase = pci_read_word(acpi, 0x40) & 0xfffc;
pm_registers = i82371xx_pm_registers;
size = ARRAY_SIZE(i82371xx_pm_registers);
break;
case PCI_DEVICE_ID_INTEL_I63XX:
pmbase = pci_read_word(sb, 0x40) & 0xfffc;
pm_registers = i63xx_pm_registers;
size = ARRAY_SIZE(i63xx_pm_registers);
break;
case 0x1234: // Dummy for non-existent functionality
printf("This southbridge does not have PMBASE.\n");
return 1;
default:
printf("Error: Dumping PMBASE on this southbridge is not (yet) supported.\n");
return 1;
}
printf("PMBASE = 0x%04x (IO)\n\n", pmbase);
for (i = 0; i < size; i++) {
switch (pm_registers[i].size) {
case 8:
printf("pmbase+0x%04x: 0x%08x (%s)\n"
" 0x%08x\n",
pm_registers[i].addr,
inl(pmbase+pm_registers[i].addr),
pm_registers[i].name,
inl(pmbase+pm_registers[i].addr+4));
break;
case 4:
printf("pmbase+0x%04x: 0x%08x (%s)\n",
pm_registers[i].addr,
inl(pmbase+pm_registers[i].addr),
pm_registers[i].name);
break;
case 2:
printf("pmbase+0x%04x: 0x%04x (%s)\n",
pm_registers[i].addr,
inw(pmbase+pm_registers[i].addr),
pm_registers[i].name);
break;
case 1:
printf("pmbase+0x%04x: 0x%02x (%s)\n",
pm_registers[i].addr,
inb(pmbase+pm_registers[i].addr),
pm_registers[i].name);
break;
}
}
return 0;
}
int main (int argc, char *argv[])
{
struct pci_access *pacc;
struct pci_dev *dev;
struct pci_filter filter;
char *msg;
uint16_t command;
int v1_1 = 0, i2c;
if (argc != 2 &&
((argc != 3) ||
(!(v1_1 = !strcmp(argv[2], "1.1")) && strcmp(argv[2], "1.0")))) {
fprintf(stderr,
"VT6307 OHCI mode config\n"
"Version 0.9\n"
"Copyright (C) 2007 Krzysztof Halasa <*****@*****.**>\n"
"\n"
"Usage: vt6307ohciver <pci_device> [ 1.0 | 1.1 ]\n");
exit(1);
}
if (iopl(3)) {
fprintf(stderr, "iopl() failed (must be root)\n");
exit(1);
}
pacc = pci_alloc();
pci_filter_init(pacc, &filter);
if ((msg = pci_filter_parse_slot(&filter, argv[1]))) {
fprintf(stderr, "Invalid pci_device\n");
exit(1);
}
filter.vendor = VENDOR_ID;
filter.device = DEVICE_ID;
pci_init(pacc);
pci_scan_bus(pacc);
for (dev = pacc->devices; dev; dev = dev->next)
if (pci_filter_match(&filter, dev))
break;
if (!dev) {
fprintf(stderr, "Device %s not found\n", argv[2]);
exit(1);
}
pci_fill_info(dev, PCI_FILL_BASES | PCI_FILL_SIZES);
if (dev->size[0] != MEM_SIZE || dev->size[1] != IO_SIZE) {
fprintf(stderr, "Unexpected MEM/IO region size, is it"
" VT6307 chip?\n");
exit(1);
}
command = pci_read_word(dev, PCI_COMMAND);
if ((command & PCI_COMMAND_IO) == 0) {
fprintf(stderr, "Device disabled, trying to enable it\n");
pci_write_word(dev, PCI_COMMAND, command | PCI_COMMAND_IO);
}
io_ports = dev->base_addr[1] & PCI_BASE_ADDRESS_IO_MASK;
i2c = (inl(io_ports + 0x20) & 0x80) ? 0 : 1;
fprintf(stderr, "I/O region #1 is at %04X\n", io_ports);
fprintf(stderr, "It seems your VT6307 chip is connected to %s "
"EEPROM\n", i2c ? "I^2C (24c01 or similar)" : "93c46");
if (argc == 3) {
/* enable direct access to pins */
outl_p(inl(io_ports) | 0x80, io_ports);
if (i2c)
write_i2c(0x22, v1_1 ? 8 : 0);
else
write_4w(0x11, v1_1 ? 8 : 0);
/* disable direct access to pins */
outl_p(0x20, io_ports + 0x20);
fprintf(stderr, "Please reboot\n");
} else
display(dev->base_addr[0] & PCI_BASE_ADDRESS_MEM_MASK);
if ((command & PCI_COMMAND_IO) == 0) {
fprintf(stderr, "Disabling device\n");
pci_write_word(dev, PCI_COMMAND, command);
}
exit(0);
}
int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
{
int i, j, size, defaults_size = 0;
const io_register_t *gpio_registers;
const gpio_default_t *gpio_defaults = NULL;
uint32_t gpio_diff;
if (show_diffs && !show_all)
printf("\n========== GPIO DIFFS ===========\n\n");
else
printf("\n============= GPIOS =============\n\n");
switch (sb->device_id) {
case PCI_DEVICE_ID_INTEL_Z68:
case PCI_DEVICE_ID_INTEL_P67:
case PCI_DEVICE_ID_INTEL_H67:
case PCI_DEVICE_ID_INTEL_Q65:
case PCI_DEVICE_ID_INTEL_QS67:
case PCI_DEVICE_ID_INTEL_Q67:
case PCI_DEVICE_ID_INTEL_B65:
case PCI_DEVICE_ID_INTEL_C202:
case PCI_DEVICE_ID_INTEL_C204:
case PCI_DEVICE_ID_INTEL_C206:
case PCI_DEVICE_ID_INTEL_H61:
gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
gpio_registers = pch_gpio_registers;
size = ARRAY_SIZE(pch_gpio_registers);
gpio_defaults = cp_pch_desktop_defaults;
defaults_size = ARRAY_SIZE(cp_pch_desktop_defaults);
break;
case PCI_DEVICE_ID_INTEL_UM67:
case PCI_DEVICE_ID_INTEL_HM65:
case PCI_DEVICE_ID_INTEL_HM67:
case PCI_DEVICE_ID_INTEL_QM67:
gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
gpio_registers = pch_gpio_registers;
size = ARRAY_SIZE(pch_gpio_registers);
gpio_defaults = cp_pch_mobile_defaults;
defaults_size = ARRAY_SIZE(cp_pch_mobile_defaults);
break;
case PCI_DEVICE_ID_INTEL_Z77:
case PCI_DEVICE_ID_INTEL_Z75:
case PCI_DEVICE_ID_INTEL_Q77:
case PCI_DEVICE_ID_INTEL_Q75:
case PCI_DEVICE_ID_INTEL_B75:
case PCI_DEVICE_ID_INTEL_H77:
case PCI_DEVICE_ID_INTEL_C216:
gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
gpio_registers = pch_gpio_registers;
size = ARRAY_SIZE(pch_gpio_registers);
gpio_defaults = pp_pch_desktop_defaults;
defaults_size = ARRAY_SIZE(pp_pch_desktop_defaults);
break;
case PCI_DEVICE_ID_INTEL_QM77:
case PCI_DEVICE_ID_INTEL_QS77:
case PCI_DEVICE_ID_INTEL_HM77:
case PCI_DEVICE_ID_INTEL_UM77:
case PCI_DEVICE_ID_INTEL_HM76:
case PCI_DEVICE_ID_INTEL_HM75:
case PCI_DEVICE_ID_INTEL_HM70:
gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
gpio_registers = pch_gpio_registers;
size = ARRAY_SIZE(pch_gpio_registers);
gpio_defaults = pp_pch_mobile_defaults;
defaults_size = ARRAY_SIZE(pp_pch_mobile_defaults);
break;
case PCI_DEVICE_ID_INTEL_ICH10R:
gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
gpio_registers = ich10_gpio_registers;
size = ARRAY_SIZE(ich10_gpio_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH9DH:
case PCI_DEVICE_ID_INTEL_ICH9DO:
case PCI_DEVICE_ID_INTEL_ICH9R:
case PCI_DEVICE_ID_INTEL_ICH9:
case PCI_DEVICE_ID_INTEL_ICH9M:
case PCI_DEVICE_ID_INTEL_ICH9ME:
gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
gpio_registers = ich9_gpio_registers;
size = ARRAY_SIZE(ich9_gpio_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH8:
case PCI_DEVICE_ID_INTEL_ICH8M:
gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
gpio_registers = ich8_gpio_registers;
size = ARRAY_SIZE(ich8_gpio_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH7:
case PCI_DEVICE_ID_INTEL_ICH7M:
case PCI_DEVICE_ID_INTEL_ICH7DH:
case PCI_DEVICE_ID_INTEL_ICH7MDH:
case PCI_DEVICE_ID_INTEL_NM10:
gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
gpio_registers = ich7_gpio_registers;
size = ARRAY_SIZE(ich7_gpio_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH6:
gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
gpio_registers = ich6_gpio_registers;
size = ARRAY_SIZE(ich6_gpio_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH5:
gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
gpio_registers = ich5_gpio_registers;
size = ARRAY_SIZE(ich5_gpio_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH4:
case PCI_DEVICE_ID_INTEL_ICH4M:
gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
gpio_registers = ich4_gpio_registers;
size = ARRAY_SIZE(ich4_gpio_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH2:
gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
gpio_registers = ich2_gpio_registers;
size = ARRAY_SIZE(ich2_gpio_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH:
case PCI_DEVICE_ID_INTEL_ICH0:
gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
gpio_registers = ich0_gpio_registers;
size = ARRAY_SIZE(ich0_gpio_registers);
break;
case PCI_DEVICE_ID_INTEL_I63XX:
gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
gpio_registers = i631x_gpio_registers;
size = ARRAY_SIZE(i631x_gpio_registers);
break;
case PCI_DEVICE_ID_INTEL_3400_DESKTOP:
case PCI_DEVICE_ID_INTEL_3400_MOBILE:
case PCI_DEVICE_ID_INTEL_P55:
case PCI_DEVICE_ID_INTEL_PM55:
case PCI_DEVICE_ID_INTEL_H55:
case PCI_DEVICE_ID_INTEL_QM57:
case PCI_DEVICE_ID_INTEL_H57:
case PCI_DEVICE_ID_INTEL_HM55:
case PCI_DEVICE_ID_INTEL_Q57:
case PCI_DEVICE_ID_INTEL_HM57:
case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF:
case PCI_DEVICE_ID_INTEL_B55_A:
case PCI_DEVICE_ID_INTEL_QS57:
case PCI_DEVICE_ID_INTEL_3400:
case PCI_DEVICE_ID_INTEL_3420:
case PCI_DEVICE_ID_INTEL_3450:
case PCI_DEVICE_ID_INTEL_B55_B:
gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
gpio_registers = i631x_gpio_registers;
size = ARRAY_SIZE(i631x_gpio_registers);
break;
case PCI_DEVICE_ID_INTEL_82371XX:
printf("This southbridge has GPIOs in the PM unit.\n");
return 1;
case 0x1234: // Dummy for non-existent functionality
printf("This southbridge does not have GPIOBASE.\n");
return 1;
default:
printf("Error: Dumping GPIOs on this southbridge is not (yet) supported.\n");
return 1;
}
printf("GPIOBASE = 0x%04x (IO)\n\n", gpiobase);
j = 0;
for (i = 0; i < size; i++) {
if (show_all)
print_reg(&gpio_registers[i]);
if (show_diffs &&
(j < defaults_size) &&
(gpio_defaults[j].addr == gpio_registers[i].addr)) {
gpio_diff = get_diff(&gpio_registers[i],
gpio_defaults[j].def);
if (gpio_diff) {
if (!show_all)
print_reg(&gpio_registers[i]);
print_diff(&gpio_registers[i],
gpio_defaults[j].def, gpio_diff);
if (!show_all)
printf("\n");
}
j++;
}
}
return 0;
}
uint16_t pci_get_vendor(uint16_t bus, uint16_t device, uint16_t function)
{
uint16_t r = pci_read_word(bus,device,function,0);
return r;
}
uint16_t pci_get_device(uint16_t bus, uint16_t device, uint16_t function)
{
uint16_t r = pci_read_word(bus,device,function,2);
return r;
}
int
pci_generic_fill_info(struct pci_dev *d, int flags)
{
struct pci_access *a = d->access;
if (flags & PCI_FILL_IDENT)
{
d->vendor_id = pci_read_word(d, PCI_VENDOR_ID);
d->device_id = pci_read_word(d, PCI_DEVICE_ID);
}
if (flags & PCI_FILL_IRQ)
d->irq = pci_read_byte(d, PCI_INTERRUPT_LINE);
if (flags & PCI_FILL_BASES)
{
int cnt = 0, i;
//bzero(d->base_addr, sizeof(d->base_addr));
memset(d->base_addr,0, sizeof(d->base_addr));
switch (d->hdrtype)
{
case PCI_HEADER_TYPE_NORMAL:
cnt = 6;
break;
case PCI_HEADER_TYPE_BRIDGE:
cnt = 2;
break;
case PCI_HEADER_TYPE_CARDBUS:
cnt = 1;
break;
}
if (cnt)
{
u16 cmd = pci_read_word(d, PCI_COMMAND);
for(i=0; i<cnt; i++)
{
u32 x = pci_read_long(d, PCI_BASE_ADDRESS_0 + i*4);
if (!x || x == (u32) ~0)
continue;
d->base_addr[i] = x;
if (x & PCI_BASE_ADDRESS_SPACE_IO)
{
if (!a->buscentric && !(cmd & PCI_COMMAND_IO))
d->base_addr[i] = 0;
}
else if (a->buscentric || (cmd & PCI_COMMAND_MEMORY))
{
if ((x & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64)
{
if (i >= cnt-1)
a->warning("%02x:%02x.%d: Invalid 64-bit address seen.", d->bus, d->dev, d->func);
else
{
u32 y = pci_read_long(d, PCI_BASE_ADDRESS_0 + (++i)*4);
#ifdef HAVE_64BIT_ADDRESS
d->base_addr[i-1] |= ((pciaddr_t) y) << 32;
#else
if (y)
{
a->warning("%02x:%02x.%d 64-bit device address ignored.", d->bus, d->dev, d->func);
d->base_addr[i-1] = 0;
}
#endif
}
}
}
else
d->base_addr[i] = 0;
}
}
}
if (flags & PCI_FILL_ROM_BASE)
{
int reg = 0;
d->rom_base_addr = 0;
switch (d->hdrtype)
{
case PCI_HEADER_TYPE_NORMAL:
reg = PCI_ROM_ADDRESS;
break;
case PCI_HEADER_TYPE_BRIDGE:
reg = PCI_ROM_ADDRESS1;
break;
}
if (reg)
{
u32 a = pci_read_long(d, reg);
if (a & PCI_ROM_ADDRESS_ENABLE)
d->rom_base_addr = a;
}
}
return flags & ~PCI_FILL_SIZES;
}
uint16_t getClassId(uint16_t bus, uint16_t device, uint16_t function)
{
uint32_t r0 = pci_read_word(bus,device,function,0xA);
return (r0 & ~0x00FF) >> 8;
}
int
pci_generic_fill_info(struct pci_dev *d, int flags)
{
struct pci_access *a = d->access;
if ((flags & (PCI_FILL_BASES | PCI_FILL_ROM_BASE)) && d->hdrtype < 0)
d->hdrtype = pci_read_byte(d, PCI_HEADER_TYPE) & 0x7f;
if (flags & PCI_FILL_IDENT)
{
d->vendor_id = pci_read_word(d, PCI_VENDOR_ID);
d->device_id = pci_read_word(d, PCI_DEVICE_ID);
}
if (flags & PCI_FILL_CLASS)
d->device_class = pci_read_word(d, PCI_CLASS_DEVICE);
if (flags & PCI_FILL_IRQ)
d->irq = pci_read_byte(d, PCI_INTERRUPT_LINE);
if (flags & PCI_FILL_BASES)
{
int cnt = 0, i;
memset(d->base_addr, 0, sizeof(d->base_addr));
switch (d->hdrtype)
{
case PCI_HEADER_TYPE_NORMAL:
cnt = 6;
break;
case PCI_HEADER_TYPE_BRIDGE:
cnt = 2;
break;
case PCI_HEADER_TYPE_CARDBUS:
cnt = 1;
break;
}
if (cnt)
{
for (i=0; i<cnt; i++)
{
u32 x = pci_read_long(d, PCI_BASE_ADDRESS_0 + i*4);
if (!x || x == (u32) ~0)
continue;
if ((x & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO)
d->base_addr[i] = x;
else
{
if ((x & PCI_BASE_ADDRESS_MEM_TYPE_MASK) != PCI_BASE_ADDRESS_MEM_TYPE_64)
d->base_addr[i] = x;
else if (i >= cnt-1)
a->warning("%04x:%02x:%02x.%d: Invalid 64-bit address seen for BAR %d.", d->domain, d->bus, d->dev, d->func, i);
else
{
u32 y = pci_read_long(d, PCI_BASE_ADDRESS_0 + (++i)*4);
#ifdef PCI_HAVE_64BIT_ADDRESS
d->base_addr[i-1] = x | (((pciaddr_t) y) << 32);
#else
if (y)
a->warning("%04x:%02x:%02x.%d 64-bit device address ignored.", d->domain, d->bus, d->dev, d->func);
else
d->base_addr[i-1] = x;
#endif
}
}
}
}
}
if (flags & PCI_FILL_ROM_BASE)
{
int reg = 0;
d->rom_base_addr = 0;
switch (d->hdrtype)
{
case PCI_HEADER_TYPE_NORMAL:
reg = PCI_ROM_ADDRESS;
break;
case PCI_HEADER_TYPE_BRIDGE:
reg = PCI_ROM_ADDRESS1;
break;
}
if (reg)
{
u32 u = pci_read_long(d, reg);
if (u != 0xffffffff)
d->rom_base_addr = u;
}
}
if (flags & (PCI_FILL_CAPS | PCI_FILL_EXT_CAPS))
flags |= pci_scan_caps(d, flags);
return flags & ~PCI_FILL_SIZES;
}
/*
* Find all suitable cards, then find their memory space and get memory information.
*/
int main()
{
struct pci_access *pci;
struct pci_dev *dev;
int i, meminfo;
u32 subvendor, subdevice;
off_t base;
int *pcimem;
int fd;
char *devname;
int fail =0, manufacturer, model;
printf("AMDMemInfo by Zuikkis <*****@*****.**>\n");
pci = pci_alloc();
pci_init(pci);
pci_scan_bus(pci);
for(dev = pci->devices; dev; dev = dev->next) {
if(dev->device_class == PCI_CLASS_DISPLAY_VGA &&
dev->vendor_id == 0x1002 &&
( dev->device_id == 0x679a || // hd7950
dev->device_id == 0x6798 || // hd7970 / r9 280x
dev->device_id == 0x679b || // hd7990
dev->device_id == 0x67b1 || // r9 290
dev->device_id == 0x67b0 || // r9 290
dev->device_id == 0x6811 || // r9 270
dev->device_id == 0x6719 || // hd6950
dev->device_id == 0x6778 || // HD6450 device id 1
dev->device_id == 0x6779 || // HD6450 device id 2
dev->device_id == 0x6819 || // hd7850
dev->device_id == 0x6818)) // hd7870
{
switch (dev->device_id) {
case 0x679a: devname="Radeon HD7950"; break;
case 0x6798: devname="Radeon HD7970 / R9 280x"; break;
case 0x679b: devname="Radeon HD7990"; break;
case 0x67b1: devname="Radeon R9 290"; break;
case 0x67b0: devname="Radeon R9 290x"; break;
case 0x6811: devname="Radeon R9 270"; break;
case 0x6818: devname="Radeon HD7870"; break;
case 0x6819: devname="Radeon HD7850"; break;
case 0x6719: devname="Radeon HD6950"; break;
case 0x6778: devname="Radeon HD6450"; break;
case 0x6779: devname="Radeon HD6450"; break;
default: devname="Unknown"; break;
}
subvendor = pci_read_word(dev, PCI_SUBSYSTEM_VENDOR_ID);
subdevice = pci_read_word(dev, PCI_SUBSYSTEM_ID);
printf( "-----------------------------------\n"
"Found card: %04x:%04x (AMD %s)\n"
"Subvendor: 0x%x\n"
"Subdevice: 0x%x\n",
dev->vendor_id, dev->device_id, devname, subvendor, subdevice);
for (i=0;i<6;i++) {
if (dev->size[i]==0x40000) {
base=(dev->base_addr[i] & 0xfffffff0);
fd = open ( "/dev/mem", O_RDONLY);
pcimem = (int *) mmap(NULL, 0x20000, PROT_READ, MAP_SHARED, fd, base);
if (pcimem == MAP_FAILED) {
fail++;
} else {
meminfo=pcimem[(0x2a00)/4];
manufacturer=(meminfo & 0xf00)>>8;
model=(meminfo & 0xf000)>>12;
printf("Memory type: ");
switch(manufacturer) {
case 1:
printf("Samsung K4G20325FD\n"); break;
case 3:
printf("Elpida EDW2032BBBG\n"); break;
case 6:
switch(model) {
case 2: printf("SK Hynix H5GQ2H24MFR\n"); break;
case 3: printf("SK Hynix H5GQ2H24AFR\n"); break;
default: printf("SK Hynix unknown model %d\n",model);
}
break;
default:
printf("Unknown manufacturer %d\n",manufacturer);
}
munmap(pcimem, 0x20000);
}
close(fd);
}
}
}
}
static void
exec_op(struct op *op, struct pci_dev *dev)
{
const char * const formats[] = { NULL, " %02x", " %04x", NULL, " %08x" };
const char * const mask_formats[] = { NULL, " %02x->(%02x:%02x)->%02x", " %04x->(%04x:%04x)->%04x", NULL, " %08x->(%08x:%08x)->%08x" };
unsigned int i, x, y;
int addr = 0;
int width = op->width;
char slot[16];
sprintf(slot, "%04x:%02x:%02x.%x", dev->domain, dev->bus, dev->dev, dev->func);
trace("%s ", slot);
if (op->cap_type)
{
struct pci_cap *cap;
cap = pci_find_cap(dev, op->cap_id, op->cap_type);
if (cap)
addr = cap->addr;
else
die("%s: %s %04x not found", slot, ((op->cap_type == PCI_CAP_NORMAL) ? "Capability" : "Extended capability"), op->cap_id);
trace(((op->cap_type == PCI_CAP_NORMAL) ? "(cap %02x @%02x) " : "(ecap %04x @%03x) "), op->cap_id, addr);
}
addr += op->addr;
trace("@%02x", addr);
/* We have already checked it when parsing, but addressing relative to capabilities can change the address. */
if (addr & (width-1))
die("%s: Unaligned access of width %d to register %04x", slot, width, addr);
if (addr + width > 0x1000)
die("%s: Access of width %d to register %04x out of range", slot, width, addr);
if (op->num_values)
{
for (i=0; i<op->num_values; i++)
{
if ((op->values[i].mask & max_values[width]) == max_values[width])
{
x = op->values[i].value;
trace(formats[width], op->values[i].value);
}
else
{
switch (width)
{
case 1:
y = pci_read_byte(dev, addr);
break;
case 2:
y = pci_read_word(dev, addr);
break;
default:
y = pci_read_long(dev, addr);
break;
}
x = (y & ~op->values[i].mask) | op->values[i].value;
trace(mask_formats[width], y, op->values[i].value, op->values[i].mask, x);
}
if (!demo_mode)
{
switch (width)
{
case 1:
pci_write_byte(dev, addr, x);
break;
case 2:
pci_write_word(dev, addr, x);
break;
default:
pci_write_long(dev, addr, x);
break;
}
}
addr += width;
}
trace("\n");
}
else
{
trace(" = ");
switch (width)
{
case 1:
x = pci_read_byte(dev, addr);
break;
case 2:
x = pci_read_word(dev, addr);
break;
default:
x = pci_read_long(dev, addr);
break;
}
printf(formats[width]+1, x);
putchar('\n');
}
}
uint16_t getDeviceID(uint16_t bus, uint16_t device, uint16_t function)
{
uint32_t r0 = pci_read_word(bus,device,function,2);
return r0;
}