void __init ixp2000_pci_init(void *sysdata)
{
external_fault = ixp2000_pci_abort_handler;
DBG("PCI: set upper mem io bits\n");
*IXP2000_PCI_ADDR_EXT = 0x0;
if (npu_is_master()) {/* master NPU */
pci_scan_bus(0, &ixp2000_ops, sysdata);
} else { /* NPU is slave */
/*
* NOTE TO HW DESIGNERS:
*
* Do NOT make boards like this which have slave devices that scan
* the bus and own devices. It is completely against the PCI spec
* as it is _NOT_ a peer to peer bus.
*/
if(machine_is_ixdp2400())
pci_scan_bus(0, &ixp2000_ops, sysdata);
}
/* enable PCI INTB */
*(IXP2000_IRQ_ENABLE_SET) = (1<<15);
*IXP2000_PCI_XSCALE_INT_ENABLE |= (1<<27) | (1<<26);
DBG("ixp200_pci_init Done\n");
}
void __init via82c505_init(void *sysdata)
{
struct pci_bus *bus;
printk(KERN_DEBUG "PCI: VIA 82c505\n");
if (!request_region(0xA8,2,"via config")) {
printk(KERN_WARNING"VIA 82c505: Unable to request region 0xA8\n");
return;
}
if (!request_region(0xCF8,8,"pci config")) {
printk(KERN_WARNING"VIA 82c505: Unable to request region 0xCF8\n");
release_region(0xA8, 2);
return;
}
/* Enable compatible Mode */
outb(0x96,0xA8);
outb(0x18,0xA9);
outb(0x93,0xA8);
outb(0xd0,0xA9);
pci_scan_bus(0, &via82c505_ops, sysdata);
#ifdef CONFIG_ARCH_SHARK
/*
* Initialize a fake pci-bus number 1 for the CyberPro
* on the vlbus
*/
bus = pci_scan_bus(1, &dummy_ops, sysdata);
#endif
}
/* --- implementations --- */
int detect_pci22(void){
unsigned int c;
char counter=0;
pacc = pci_alloc(); /* Get the pci_access structure */
pci_init(pacc); /* Initialize the PCI library */
pci_scan_bus(pacc); /* We want to get the list of devices */
/* Iterate over all PCI devices */
for(pci22_dev=pacc->devices; pci22_dev; pci22_dev=pci22_dev->next){
pci_fill_info(pci22_dev, PCI_FILL_IDENT | PCI_FILL_BASES);
// Detect the specified device
if( (pci22_dev->vendor_id == PCI22_PCI_VENDOR_ID) &&
(pci22_dev->device_id == PCI22_PCI_DEVICE_ID)
){
break;
}
}
if (pci22_dev==NULL){
printf("\n\nERROR: PCI22 card not detected\n\n\n");
exit(0);
}
printf("\n\nPCI22 card detected on %02x:%02x.%d\nVendorID=%04x DeviceID=%04x irq=%d\n",
pci22_dev->bus,pci22_dev->dev,
pci22_dev->func,pci22_dev->vendor_id,
pci22_dev->device_id,
pci22_dev->irq);
printf("\n\n--- Baseaddresses ---\n");
printf("BAR1 %x\n",pci22_dev->base_addr[0]);
printf("BAR2 %x\n",pci22_dev->base_addr[1]);
printf("BAR3 %x\n",pci22_dev->base_addr[2]);
printf("BAR4 %x\n",pci22_dev->base_addr[3]);
printf("BAR5 %x\n",pci22_dev->base_addr[4]);
printf("BAR6 %x\n",pci22_dev->base_addr[6]);
printf("\n");
//printPCIDevice(pci22_dev);
/* The baseaddress of the COM20022 is at BAR2 */
//g_pci22dipswitch = pci22_dev->base_addr[1]; //Nonworking
g_pci22base = pci22_dev->base_addr[2];
/* Close everything */
pci_cleanup(pacc);
return 0;
}
static int __init pcibios_init(void)
{
struct pci_controller *pci_ctrl;
struct pci_bus *bus;
int next_busno = 0, i;
printk("PCI: Probing PCI hardware\n");
/* Scan all of the recorded PCI controllers. */
for (pci_ctrl = pci_ctrl_head; pci_ctrl; pci_ctrl = pci_ctrl->next) {
pci_ctrl->last_busno = 0xff;
bus = pci_scan_bus(pci_ctrl->first_busno, pci_ctrl->ops,
pci_ctrl);
if (pci_ctrl->io_resource.flags) {
unsigned long offs;
offs = (unsigned long)pci_ctrl->io_space.base;
pci_ctrl->io_resource.start += offs;
pci_ctrl->io_resource.end += offs;
bus->resource[0] = &pci_ctrl->io_resource;
}
for (i = 0; i < 3; ++i)
if (pci_ctrl->mem_resources[i].flags)
bus->resource[i+1] =&pci_ctrl->mem_resources[i];
pci_ctrl->bus = bus;
pci_ctrl->last_busno = bus->subordinate;
if (next_busno <= pci_ctrl->last_busno)
next_busno = pci_ctrl->last_busno+1;
}
pci_bus_count = next_busno;
return platform_pcibios_fixup();
}
static int __init l4vpci_x86_init(void)
{
struct pci_dev *dev = NULL;
struct pci_bus *bus;
struct pci_sysdata *sd = kzalloc(sizeof(*sd), GFP_KERNEL);
if (!sd)
return -ENOMEM;
bus = pci_scan_bus(0, &l4vpci_ops, sd);
if (!bus) {
pr_err("Failed to scan PCI bus\n");
return -ENODEV;
}
pci_bus_add_devices(bus);
pr_info("l4vPCI: Using L4-IO for IRQ routing\n");
for_each_pci_dev(dev)
l4vpci_irq_enable(dev);
pcibios_resource_survey();
return 0;
}
struct pci_bus * __init via82c505_scan_bus(int nr, struct pci_sys_data *sysdata)
{
if (nr == 0)
return pci_scan_bus(0, &via82c505_ops, sysdata);
return NULL;
}
void __init pcibios_init(void)
{
struct pci_channel *p;
struct pci_bus *bus;
int busno;
/* assign resources */
busno=0;
for (p= mips_pci_channels; p->pci_ops != NULL; p++) {
busno = pciauto_assign_resources(busno, p) + 1;
}
/* scan the buses */
busno = 0;
for (p= mips_pci_channels; p->pci_ops != NULL; p++) {
bus = pci_scan_bus(busno, p->pci_ops, p);
busno = bus->subordinate+1;
}
/* fixup irqs (board specific routines) */
pcibios_fixup_irqs();
/*
* should we do a fixup of ioport_resource and iomem_resource
* based on mips_pci_channels?
* Let us wait and see if this is a common need and whether there
* are exceptions. Until then, each board should adjust them
* perhaps in their setup() function.
*/
}
static int __init pcibios_init(void)
{
struct pci_channel *p;
struct pci_bus *bus;
int busno;
#if 1
/* assign resources */
busno = 0;
for (p = board_pci_channels; p->pci_ops != NULL; p++) {
busno = pciauto_assign_resources(busno, p) + 1;
}
#endif
/* scan the buses */
busno = 0;
for (p= board_pci_channels; p->pci_ops != NULL; p++) {
bus = pci_scan_bus(busno, p->pci_ops, p);
busno = bus->subordinate+1;
}
/* board-specific fixups */
pcibios_fixup_irqs();
return 0;
}
/*
* Initialization. Try all known PCI access methods. Note that we support
* using both PCI BIOS and direct access: in such cases, we use I/O ports
* to access config space, but we still keep BIOS order of cards to be
* compatible with 2.0.X. This should go away some day.
*/
static int __init pcibios_init(void)
{
ioport_resource.start = 0xA0000000;
ioport_resource.end = 0xDFFFFFFF;
iomem_resource.start = 0xA0000000;
iomem_resource.end = 0xDFFFFFFF;
if (insert_resource(&iomem_resource, &pci_iomem_resource) < 0)
panic("Unable to insert PCI IOMEM resource\n");
if (insert_resource(&ioport_resource, &pci_ioport_resource) < 0)
panic("Unable to insert PCI IOPORT resource\n");
if (!pci_probe)
return 0;
if (pci_check_direct() < 0) {
printk(KERN_WARNING "PCI: No PCI bus detected\n");
return 0;
}
printk(KERN_INFO "PCI: Probing PCI hardware [mempage %08x]\n",
MEM_PAGING_REG);
pci_root_bus = pci_scan_bus(0, &pci_direct_ampci, NULL);
pcibios_irq_init();
pcibios_fixup_irqs();
pcibios_resource_survey();
return 0;
}
void __init ks8695p_init(void *sysdata)
{
#ifdef DEBUG_THIS
printk(KERN_INFO "%s\n", __FUNCTION__);
#endif
/* note that we need a stage 1 initialization in .S file to set 0x202c,
* before the stage 2 initialization here
*/
KS8695_WRITE(KS8695_202C, 0x00010001); /* stage 1 initialization, subid, subdevice = 0x0001 */
/* stage 2 initialization */
KS8695_WRITE(KS8695_2204, 0x40000000); /* prefetch limits with 16 words, retru enable */
/* configure memory mapping */
KS8695_WRITE(KS8695_2208, KS8695P_PCIBG_MEM_BASE);
//KS8695_WRITE(KS8695_220C, PMBAC_TRANS_ENABLE); /* enable memory address translation */
KS8695_WRITE(KS8695_2210, KS8695P_PCI_MEM_MASK); /* mask bits */
KS8695_WRITE(KS8695_2214, KS8695P_PCI_MEM_BASE); /* physical memory address */
/* configure IO mapping */
KS8695_WRITE(KS8695_2218, KS8695P_PCIBG_IO_BASE);
//KS8695_WRITE(KS8695_221C, PMBAC_TRANS_ENABLE); /* enable IO address translation */
KS8695_WRITE(KS8695_2220, KS8695P_PCI_IO_MASK); /* mask bits */
KS8695_WRITE(KS8695_2224, KS8695P_PCI_IO_BASE);
ks8695p_configure_interrupt();
pci_scan_bus(0, &ks8695p_ops, sysdata);
}
static void __init pirq_peer_trick(void)
{
struct irq_routing_table *rt = pirq_table;
u8 busmap[256];
int i;
struct irq_info *e;
memset(busmap, 0, sizeof(busmap));
for(i=0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
e = &rt->slots[i];
#ifdef DEBUG
{
int j;
DBG(KERN_DEBUG "%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot);
for(j=0; j<4; j++)
DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
DBG("\n");
}
#endif
busmap[e->bus] = 1;
}
for(i = 1; i < 256; i++) {
if (!busmap[i] || pci_find_bus(0, i))
continue;
if (pci_scan_bus(i, &pci_root_ops, NULL))
printk(KERN_INFO "PCI: Discovered primary peer bus %02x [IRQ]\n", i);
}
pcibios_last_bus = -1;
}
void __init pcibios_init(void)
{
struct pci_channel *p;
struct pci_bus *bus;
int busno;
#ifdef CONFIG_PCI_AUTO
/* assign resources */
busno=0;
for (p= mips_pci_channels; p->pci_ops != NULL; p++) {
busno = pciauto_assign_resources(busno, p) + 1;
}
#endif
/* scan the buses */
busno = 0;
for (p= mips_pci_channels; p->pci_ops != NULL; p++) {
bus = pci_scan_bus(busno, p->pci_ops, p);
busno = bus->subordinate+1;
}
/* machine dependent fixups */
pcibios_fixup();
/* fixup irqs (board specific routines) */
pcibios_fixup_irqs();
}
static void __init pirq_peer_trick(void)
{
struct irq_routing_table *rt = pirq_table;
u8 busmap[256];
int i;
struct irq_info *e;
memset(busmap, 0, sizeof(busmap));
for(i=0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
e = &rt->slots[i];
#ifdef DEBUG
{
int j;
DBG("%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot);
for(j=0; j<4; j++)
DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
DBG("\n");
}
#endif
busmap[e->bus] = 1;
}
for(i=1; i<256; i++)
/*
* It might be a secondary bus, but in this case its parent is already
* known (ascending bus order) and therefore pci_scan_bus returns immediately.
*/
if (busmap[i] && pci_scan_bus(i, pci_root_bus->ops, NULL))
printk(KERN_INFO "PCI: Discovered primary peer bus %02x [IRQ]\n", i);
pcibios_last_bus = -1;
}
void pci_scan(pci_func_t f, int type) {
pci_scan_bus(f, type, 0);
if (!pci_read_field(0, PCI_HEADER_TYPE, 1)) {
return;
}
for (int func = 1; func < 8; ++func) {
uint32_t dev = pci_box_device(0, 0, func);
if (pci_read_field(dev, PCI_VENDOR_ID, 2) != PCI_NONE) {
pci_scan_bus(f, type, func);
} else {
break;
}
}
}
void pci_scan_func(pci_func_t f, int type, int bus, int slot, int func) {
uint32_t dev = pci_box_device(bus, slot, func);
if (type == -1 || type == pci_find_type(dev)) {
pci_scan_hit(f, dev);
}
if (pci_find_type(dev) == PCI_TYPE_BRIDGE) {
pci_scan_bus(f, type, pci_read_field(dev, PCI_SECONDARY_BUS, 1));
}
}
static struct pci_bus *soc_pci_scan_bus(int nr, struct pci_sys_data *sys)
{
#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 3, 0)
return pci_scan_bus(sys->busnr, &soc_pcie_ops, sys);
#else
return pci_scan_root_bus(NULL, sys->busnr, &soc_pcie_ops, sys,
&sys->resources);
#endif
}
static int __init pcibios_init(void)
{
/* The VISWS supports configuration access type 1 only */
pci_probe = (pci_probe | PCI_PROBE_CONF1) &
~(PCI_PROBE_BIOS | PCI_PROBE_CONF2);
pci_bus0 = li_pcib_read16(LI_PCI_BUSNUM) & 0xff;
pci_bus1 = li_pcia_read16(LI_PCI_BUSNUM) & 0xff;
printk(KERN_INFO "PCI: Lithium bridge A bus: %u, "
"bridge B (PIIX4) bus: %u\n", pci_bus1, pci_bus0);
raw_pci_ops = &pci_direct_conf1;
pci_scan_bus(pci_bus0, &pci_root_ops, NULL);
pci_scan_bus(pci_bus1, &pci_root_ops, NULL);
pci_fixup_irqs(visws_swizzle, visws_map_irq);
pcibios_resource_survey();
return 0;
}
/* Exported interface */
int
pci_init(void)
{
static struct pci_bus root_bus;
memset(&root_bus, 0, sizeof(root_bus));
if (platform_pci_init() < 0)
panic("pci: unable to initial PCI\n");
return pci_scan_bus(&root_bus);
}
void
pci_init (void)
{
list_init (&devices);
list_init (&int_devices);
num_pci_pages = 0;
pci_scan_bus (0);
pci_print_stats ();
}
void __init pcibios_init(void)
{
/*
* XXX These values below need to change
*/
ioport_resource.start = 0xe0000000;
ioport_resource.end = 0xe0000000 + 0x20000000 - 1;
iomem_resource.start = 0xc0000000;
iomem_resource.end = 0xc0000000 + 0x20000000 - 1;
pci_scan_bus(0, &titan_pci_ops, NULL);
}
void __init pcibios_init(void)
{
printk("PCI: Probing PCI hardware on host bus 0.\n");
switch (mips_revision_corid) {
case MIPS_REVISION_CORID_QED_RM5261:
case MIPS_REVISION_CORID_CORE_LV:
case MIPS_REVISION_CORID_CORE_FPGA:
/*
* Due to a bug in the Galileo system controller, we need
* to setup the PCI BAR for the Galileo internal registers.
* This should be done in the bios/bootprom and will be
* fixed in a later revision of YAMON (the MIPS boards
* boot prom).
*/
GT_WRITE(GT_PCI0_CFGADDR_OFS,
(0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */
(0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */
(0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/
((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/
GT_PCI0_CFGADDR_CONFIGEN_BIT );
/* Perform the write */
GT_WRITE( GT_PCI0_CFGDATA_OFS, PHYSADDR(GT64120_BASE));
pci_scan_bus(0, >64120_pci_ops, NULL);
break;
case MIPS_REVISION_CORID_BONITO64:
case MIPS_REVISION_CORID_CORE_20K:
pci_scan_bus(0, &bonito64_pci_ops, NULL);
break;
case MIPS_REVISION_CORID_CORE_MSC:
pci_scan_bus(0, &msc_pci_ops, NULL);
break;
}
malta_fixup();
}
void __init pcibios_init(void)
{
struct pci_ops *ops = &bridge_pci_ops;
int i;
ioport_resource.end = ~0UL;
iomem_resource.end = ~0UL;
for (i=0; i<num_bridges; i++) {
printk("PCI: Probing PCI hardware on host bus %2d.\n", i);
pci_scan_bus(i, ops, NULL);
}
}
static int
pci_connect( device_t *igb_dev )
{
struct pci_access *pacc;
struct pci_dev *dev;
int err;
char devpath[IGB_BIND_NAMESZ];
memset( igb_dev, 0, sizeof(device_t));
pacc = pci_alloc();
pci_init(pacc);
pci_scan_bus(pacc);
for (dev=pacc->devices; dev; dev=dev->next)
{
pci_fill_info(dev, PCI_FILL_IDENT | PCI_FILL_BASES | PCI_FILL_CLASS);
igb_dev->pci_vendor_id = dev->vendor_id;
igb_dev->pci_device_id = dev->device_id;
igb_dev->domain = dev->domain;
igb_dev->bus = dev->bus;
igb_dev->dev = dev->dev;
igb_dev->func = dev->func;
snprintf
(devpath, IGB_BIND_NAMESZ, "%04x:%02x:%02x.%d", dev->domain,
dev->bus, dev->dev, dev->func );
err = igb_probe( igb_dev );
if (err) {
continue;
}
printf ("attaching to %s\n", devpath);
err = igb_attach( devpath, igb_dev );
if (err) {
printf ("attach failed! (%s)\n", strerror(errno));
continue;
}
goto out;
}
pci_cleanup(pacc);
return ENXIO;
out:
pci_cleanup(pacc);
return 0;
}
int pci_init_common(void)
{
if (pacc != NULL) {
msg_perr("%s: Tried to allocate a new PCI context, but there is still an old one!\n"
"Please report a bug at [email protected]\n", __func__);
return 1;
}
pacc = pci_alloc(); /* Get the pci_access structure */
pci_init(pacc); /* Initialize the PCI library */
if (register_shutdown(pcidev_shutdown, NULL))
return 1;
pci_scan_bus(pacc); /* We want to get the list of devices */
return 0;
}
static struct pci_bus __init *
kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
{
struct pci_bus *bus;
if (nr == 0) {
bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
} else {
bus = NULL;
BUG();
}
return bus;
}
static struct pci_bus __init *
dove_pcie_scan_bus(int nr, struct pci_sys_data *sys)
{
struct pci_bus *bus;
if (nr < num_pcie_ports) {
bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
} else {
bus = NULL;
BUG();
}
return bus;
}
void __init
nautilus_init_pci(void)
{
struct pci_controller *hose = hose_head;
struct pci_bus *bus;
struct pci_dev *irongate;
unsigned long bus_align, bus_size, pci_mem;
unsigned long memtop = max_low_pfn << PAGE_SHIFT;
/* Scan our single hose. */
bus = pci_scan_bus(0, alpha_mv.pci_ops, hose);
if (!bus)
return;
hose->bus = bus;
pcibios_claim_one_bus(bus);
irongate = pci_get_bus_and_slot(0, 0);
bus->self = irongate;
bus->resource[0] = &irongate_io;
bus->resource[1] = &irongate_mem;
pci_bus_size_bridges(bus);
/* IO port range. */
bus->resource[0]->start = 0;
bus->resource[0]->end = 0xffff;
/* Set up PCI memory range - limit is hardwired to 0xffffffff,
base must be at aligned to 16Mb. */
bus_align = bus->resource[1]->start;
bus_size = bus->resource[1]->end + 1 - bus_align;
if (bus_align < 0x1000000UL)
bus_align = 0x1000000UL;
pci_mem = (0x100000000UL - bus_size) & -bus_align;
bus->resource[1]->start = pci_mem;
bus->resource[1]->end = 0xffffffffUL;
if (request_resource(&iomem_resource, bus->resource[1]) < 0)
printk(KERN_ERR "Failed to request MEM on hose 0\n");
if (pci_mem < memtop)
memtop = pci_mem;
if (memtop > alpha_mv.min_mem_address) {
free_reserved_area(__va(alpha_mv.min_mem_address),
__va(memtop), -1, NULL);
printk("nautilus_init_pci: %ldk freed\n",
(memtop - alpha_mv.min_mem_address) >> 10);
}
struct pci_bus * __devinit pcibios_scan_root(int busnum)
{
struct pci_bus *bus = NULL;
while ((bus = pci_find_next_bus(bus)) != NULL) {
if (bus->number == busnum) {
/* Already scanned */
return bus;
}
}
printk("PCI: Probing PCI hardware (bus %02x)\n", busnum);
return pci_scan_bus(busnum, &pci_root_ops, NULL);
}
void __init
nautilus_init_pci(void)
{
struct pci_controller *hose = hose_head;
struct pci_bus *bus;
struct pci_dev *irongate;
unsigned long bus_align, bus_size, pci_mem;
unsigned long memtop = max_low_pfn << PAGE_SHIFT;
/* */
bus = pci_scan_bus(0, alpha_mv.pci_ops, hose);
hose->bus = bus;
pcibios_claim_one_bus(bus);
irongate = pci_get_bus_and_slot(0, 0);
bus->self = irongate;
bus->resource[1] = &irongate_mem;
pci_bus_size_bridges(bus);
/* */
bus->resource[0]->start = 0;
bus->resource[0]->end = 0xffff;
/*
*/
bus_align = bus->resource[1]->start;
bus_size = bus->resource[1]->end + 1 - bus_align;
if (bus_align < 0x1000000UL)
bus_align = 0x1000000UL;
pci_mem = (0x100000000UL - bus_size) & -bus_align;
bus->resource[1]->start = pci_mem;
bus->resource[1]->end = 0xffffffffUL;
if (request_resource(&iomem_resource, bus->resource[1]) < 0)
printk(KERN_ERR "Failed to request MEM on hose 0\n");
if (pci_mem < memtop)
memtop = pci_mem;
if (memtop > alpha_mv.min_mem_address) {
free_reserved_mem(__va(alpha_mv.min_mem_address),
__va(memtop));
printk("nautilus_init_pci: %ldk freed\n",
(memtop - alpha_mv.min_mem_address) >> 10);
}
static int __init l4vpci_init(void)
{
struct pci_dev *dev = NULL;
#ifdef CONFIG_ARM
struct pci_sys_data *sd;
#else
struct pci_sysdata *sd;
#endif
int err;
L4XV_V(f);
vbus = l4re_get_env_cap("vbus");
if (l4_is_invalid_cap(vbus))
return -ENOENT;
L4XV_L(f);
err = l4vbus_get_device_by_hid(vbus, 0, &root_bridge, "PNP0A03", 0, 0);
if (err < 0) {
printk(KERN_INFO "PCI: no root bridge found, no PCI\n");
L4XV_U(f);
return err;
}
L4XV_U(f);
printk(KERN_INFO "PCI: L4 root bridge is device %lx\n", root_bridge);
sd = kzalloc(sizeof(*sd), GFP_KERNEL);
if (!sd)
return -ENOMEM;
pci_scan_bus(0, &l4vpci_ops, sd);
printk(KERN_INFO "PCI: Using L4-IO for IRQ routing\n");
for_each_pci_dev(dev)
l4vpci_irq_enable(dev);
#ifdef CONFIG_X86
pcibios_resource_survey();
#endif
return 0;
}
