void serial_init (void)
{
#if 0
uint32 clock_divisor = 115200 / baudrate;
uint8 cfg;
uint8 a;
uint16 devfn = 7 << 3;
if (serial_init_done)
return;
/* Enter configuration mode */
cfg = pci_read_cfg_byte (0, devfn, 0x85);
pci_write_cfg_byte (0, devfn, 0x85, cfg | 0x02);
/* Set serial port COM1 as 3F8 */
out_byte (0x3F0, 0xE7);
out_byte (0x3f1, 0xfe);
/* Set serial port COM2 as 2F8 */
out_byte (0x3f0, 0xe8);
out_byte (0x3f1, 0xeb);
/* Enable */
out_byte (0x3f0, 0xe2);
a = in_byte (0x3f1);
a |= 0xc;
out_byte (0x3f0, 0xe2);
out_byte (0x3f1, a);
/* Reset the configuration mode */
pci_write_cfg_byte (0, devfn, 0x85, cfg);
#endif
ComPort1 = 0x3F8;
/* Disable interrupts */
COM_WRITE_BYTE (INTERRUPT_ENABLE, 0x00);
/* Set baud rate */
/* COM_WRITE_BYTE(LINE_CONTROL, 0x83); */
/* COM_WRITE_BYTE(DIVISOR_LATCH_LSB, (uint8)(clock_divisor & 0xFF)); */
/* COM_WRITE_BYTE(DIVISOR_LATCH_MSB, (uint8)(clock_divisor >> 8)); */
/* __asm("eieio"); */
/* Set 8-N-1 */
COM_WRITE_BYTE (LINE_CONTROL, 0x03);
__asm ("eieio");
/* Disable FIFO */
COM_WRITE_BYTE (MODEM_CONTROL, 0x03);
COM_WRITE_BYTE (FIFO_CONTROL, 0x07);
__asm ("eieio");
serial_init_done = 1;
}
void via_init_irq_routing(uint8 irq_map[])
{
char *s;
uint8 level_edge_bits = 0xf;
/* Set irq routings */
pci_write_cfg_byte(0, 7<<3, 0x55, irq_map[0]<<4);
pci_write_cfg_byte(0, 7<<3, 0x56, irq_map[1] | irq_map[2]<<4);
pci_write_cfg_byte(0, 7<<3, 0x57, irq_map[3]<<4);
/*
* Gather level/edge bits
* Default is to assume level triggered
*/
s = getenv("pci_irqa_select");
if (s && strcmp(s, "level") == 0)
level_edge_bits &= ~0x01;
s = getenv("pci_irqb_select");
if (s && strcmp(s, "level") == 0)
level_edge_bits &= ~0x02;
s = getenv("pci_irqc_select");
if (s && strcmp(s, "level") == 0)
level_edge_bits &= ~0x04;
s = getenv("pci_irqd_select");
if (s && strcmp(s, "level") == 0)
level_edge_bits &= ~0x08;
PRINTF("IRQ map\n");
PRINTF("%d: %s\n", irq_map[0], level_edge_bits&0x1 ? "edge" : "level");
PRINTF("%d: %s\n", irq_map[1], level_edge_bits&0x2 ? "edge" : "level");
PRINTF("%d: %s\n", irq_map[2], level_edge_bits&0x4 ? "edge" : "level");
PRINTF("%d: %s\n", irq_map[3], level_edge_bits&0x8 ? "edge" : "level");
pci_write_cfg_byte(0, 7<<3, 0x54, level_edge_bits);
PRINTF("%02x %02x %02x %02x\n", pci_read_cfg_byte(0, 7<<3, 0x54),
pci_read_cfg_byte(0, 7<<3, 0x55), pci_read_cfg_byte(0, 7<<3, 0x56),
pci_read_cfg_byte(0, 7<<3, 0x57));
}
static void flash_to_mem(void)
{
unsigned char x;
flash_xd_nest --;
if (flash_xd_nest == 0)
{
DEBUGF("Flash on memory bus\n");
x = pci_read_cfg_byte(0, 0, 0x74);
pci_write_cfg_byte(0, 0, 0x74, x&0xFE);
}
}
static void flash_to_xd(void)
{
unsigned char x;
flash_xd_nest ++;
if (flash_xd_nest == 1)
{
DEBUGF("Flash on XD\n");
x = pci_read_cfg_byte(0, 0, 0x74);
pci_write_cfg_byte(0, 0, 0x74, x|1);
}
}
void via_init_afterscan(void)
{
/* Modify IDE controller setup */
pci_write_cfg_byte(0, 7<<3|1, PCI_LATENCY_TIMER, 0x20);
pci_write_cfg_byte(0, 7<<3|1, PCI_COMMAND, PCI_COMMAND_IO|PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER);
pci_write_cfg_byte(0, 7<<3|1, PCI_INTERRUPT_LINE, 0xff);
pci_write_cfg_byte(0, 7<<3|1, 0x40, 0x0b); /* FIXME: Might depend on drives connected */
pci_write_cfg_byte(0, 7<<3|1, 0x41, 0x42); /* FIXME: Might depend on drives connected */
pci_write_cfg_byte(0, 7<<3|1, 0x43, 0x05);
pci_write_cfg_byte(0, 7<<3|1, 0x44, 0x18);
pci_write_cfg_byte(0, 7<<3|1, 0x45, 0x10);
pci_write_cfg_byte(0, 7<<3|1, 0x4e, 0x22); /* FIXME: Not documented, but set in PC bios */
pci_write_cfg_byte(0, 7<<3|1, 0x4f, 0x20); /* FIXME: Not documented */
/* Modify some values in the USB controller */
pci_write_cfg_byte(0, 7<<3|2, 0x05, 0x17);
pci_write_cfg_byte(0, 7<<3|2, 0x06, 0x01);
pci_write_cfg_byte(0, 7<<3|2, 0x41, 0x12);
pci_write_cfg_byte(0, 7<<3|2, 0x42, 0x03);
pci_write_cfg_byte(0, 7<<3|2, PCI_LATENCY_TIMER, 0x40);
pci_write_cfg_byte(0, 7<<3|3, 0x05, 0x17);
pci_write_cfg_byte(0, 7<<3|3, 0x06, 0x01);
pci_write_cfg_byte(0, 7<<3|3, 0x41, 0x12);
pci_write_cfg_byte(0, 7<<3|3, 0x42, 0x03);
pci_write_cfg_byte(0, 7<<3|3, PCI_LATENCY_TIMER, 0x40);
}
