Ejemplos de pcie_mdioread en C++ (Cpp)

Ejemplo n.º 1

Archivo: nicpci.c Proyecto: 3sOx/asuswrt-merlin

uint32
pcicore_pcieserdesreg(void *pch, uint32 mdioslave, uint32 offset, uint32 mask, uint32 val)
{
	uint32 reg_val = 0;
	pcicore_info_t *pi = (pcicore_info_t *)pch;

	if (mask) {
		pcie_mdiowrite(pi, mdioslave, offset, val);
	}

	if (pcie_mdioread(pi, mdioslave, offset, &reg_val))
		reg_val = 0xFFFFFFFF;

	return reg_val;
}

Ejemplo n.º 2

Archivo: nicpci.c Proyecto: ariavie/bcm

/* Needs to happen when coming out of 'standby'/'hibernate' */
static void
pcie_war_serdes(pcicore_info_t *pi)
{
	uint32 w = 0;

	/* PR43448: program the correct polarity and disable future polarity inversions */
	if (pi->pcie_polarity != 0)
		pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CTRL, pi->pcie_polarity);

	/* PR42767 workaround start: modify the SERDESS PLL control register */
	pcie_mdioread(pi, MDIODATA_DEV_PLL, SERDES_PLL_CTRL, &w);
	if (w & PLL_CTRL_FREQDET_EN) {
		w &= ~PLL_CTRL_FREQDET_EN;
		pcie_mdiowrite(pi, MDIODATA_DEV_PLL, SERDES_PLL_CTRL, w);
	}
}

Ejemplo n.º 3

Archivo: nicpci.c Proyecto: ariavie/bcm

uint32
pcicore_pcieserdesreg(void *pch, uint32 mdioslave, uint32 offset, uint32 mask, uint32 val)
{
	uint32 reg_val = 0;
	pcicore_info_t *pi = (pcicore_info_t *)pch;

	if (mask) {
		PCI_ERROR(("PCIEMDIOREG: 0x%x writeval  0x%x\n", offset, val));
		pcie_mdiowrite(pi, mdioslave, offset, val);
	}

	if (pcie_mdioread(pi, mdioslave, offset, &reg_val))
		reg_val = 0xFFFFFFFF;
	PCI_ERROR(("PCIEMDIOREG: dev 0x%x offset 0x%x read 0x%x\n", mdioslave, offset, reg_val));

	return reg_val;
}

Ejemplo n.º 4

Archivo: nicpci.c Proyecto: ariavie/bcm

/* Dump PCIE PLP/DLLP/TLP  diagnostic registers */
int
pcicore_dump_pcieregs(void *pch, struct bcmstrbuf *b)
{
	pcicore_info_t *pi = (pcicore_info_t *)pch;
	sbpcieregs_t *pcieregs = pi->regs.pcieregs;
	si_t *sih = pi->sih;
	uint reg_val = 0;
	char bitfield_dump_buf[BITFIELD_DUMP_SIZE];

	bcm_bprintf(b, "PLPRegs \t");
	bcmdumpfields(si_pcie_readreg, (void *)(uintptr)pi->sih, PCIE_PCIEREGS,
		(struct fielddesc *)(uintptr)pcie_plp_regdesc,
		bitfield_dump_buf, BITFIELD_DUMP_SIZE);
	bcm_bprintf(b, "%s", bitfield_dump_buf);
	bzero(bitfield_dump_buf, BITFIELD_DUMP_SIZE);
	bcm_bprintf(b, "\n");
	bcm_bprintf(b, "DLLPRegs \t");
	bcmdumpfields(si_pcie_readreg, (void *)(uintptr)pi->sih, PCIE_PCIEREGS,
		(struct fielddesc *)(uintptr)pcie_dllp_regdesc,
		bitfield_dump_buf, BITFIELD_DUMP_SIZE);
	bcm_bprintf(b, "%s", bitfield_dump_buf);
	bzero(bitfield_dump_buf, BITFIELD_DUMP_SIZE);
	bcm_bprintf(b, "\n");
	bcm_bprintf(b, "TLPRegs \t");
	bcmdumpfields(si_pcie_readreg, (void *)(uintptr)pi->sih, PCIE_PCIEREGS,
		(struct fielddesc *)(uintptr)pcie_tlp_regdesc,
		bitfield_dump_buf, BITFIELD_DUMP_SIZE);
	bcm_bprintf(b, "%s", bitfield_dump_buf);
	bzero(bitfield_dump_buf, BITFIELD_DUMP_SIZE);
	bcm_bprintf(b, "\n");

	/* enable mdio access to SERDES */
	W_REG(pi->osh, (&pcieregs->mdiocontrol), MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL);

	bcm_bprintf(b, "SERDES regs \n");
	if (sih->buscorerev >= 10) {
		pcie_mdioread(pi, MDIO_DEV_IEEE0, 0x2, &reg_val);
		bcm_bprintf(b, "block IEEE0, offset 2: 0x%x\n", reg_val);
		pcie_mdioread(pi, MDIO_DEV_IEEE0, 0x3, &reg_val);
		bcm_bprintf(b, "block IEEE0, offset 2: 0x%x\n", reg_val);
		pcie_mdioread(pi, MDIO_DEV_IEEE1, 0x08, &reg_val);
		bcm_bprintf(b, "block IEEE1, lanestatus: 0x%x\n", reg_val);
		pcie_mdioread(pi, MDIO_DEV_IEEE1, 0x0a, &reg_val);
		bcm_bprintf(b, "block IEEE1, lanestatus2: 0x%x\n", reg_val);
		pcie_mdioread(pi, MDIO_DEV_BLK4, 0x16, &reg_val);
		bcm_bprintf(b, "MDIO_DEV_BLK4, lanetest0: 0x%x\n", reg_val);
		pcie_mdioread(pi, MDIO_DEV_TXPLL, 0x11, &reg_val);
		bcm_bprintf(b, "MDIO_DEV_TXPLL, pllcontrol: 0x%x\n", reg_val);
		pcie_mdioread(pi, MDIO_DEV_TXPLL, 0x12, &reg_val);
		bcm_bprintf(b, "MDIO_DEV_TXPLL, plltimer1: 0x%x\n", reg_val);
		pcie_mdioread(pi, MDIO_DEV_TXPLL, 0x13, &reg_val);
		bcm_bprintf(b, "MDIO_DEV_TXPLL, plltimer2: 0x%x\n", reg_val);
		pcie_mdioread(pi, MDIO_DEV_TXPLL, 0x14, &reg_val);
		bcm_bprintf(b, "MDIO_DEV_TXPLL, plltimer3: 0x%x\n", reg_val);
		pcie_mdioread(pi, MDIO_DEV_TXPLL, 0x17, &reg_val);
		bcm_bprintf(b, "MDIO_DEV_TXPLL, freqdetcounter: 0x%x\n", reg_val);
	} else {
		pcie_mdioread(pi, MDIODATA_DEV_RX, SERDES_RX_TIMER1, &reg_val);
		bcm_bprintf(b, "rxtimer1 0x%x ", reg_val);
		pcie_mdioread(pi, MDIODATA_DEV_RX, SERDES_RX_CDR, &reg_val);
		bcm_bprintf(b, "rxCDR 0x%x ", reg_val);
		pcie_mdioread(pi, MDIODATA_DEV_RX, SERDES_RX_CDRBW, &reg_val);
		bcm_bprintf(b, "rxCDRBW 0x%x\n", reg_val);
	}

	/* disable mdio access to SERDES */
	W_REG(pi->osh, (&pcieregs->mdiocontrol), 0);

	return 0;
}