phStatus_t phhalHw_Rd70x_ReadFifo(
phhalHw_Rd70x_DataParams_t * pDataParams,
uint16_t wBufSize,
uint8_t * pData,
uint16_t * pLength
)
{
phStatus_t PH_MEMLOC_REM status;
phStatus_t PH_MEMLOC_REM statusTmp;
uint8_t PH_MEMLOC_COUNT bIndex;
uint8_t PH_MEMLOC_COUNT bFifoLen;
/* read out the FiFo Length register */
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_Rd70x_ReadRegister(pDataParams, PHHAL_HW_RD70X_REG_FIFO_LENGTH, &bFifoLen));
/* check for buffer overflow */
if (bFifoLen > (uint8_t)wBufSize)
{
/* read maximum possible number of bytes */
bFifoLen = (uint8_t)wBufSize;
/* return buffer overflow status */
status = PH_ERR_BUFFER_OVERFLOW;
}
else
{
/* Buffer is big enough */
status = PH_ERR_SUCCESS;
}
/* Read each single data byte */
for (bIndex = 0; bIndex < bFifoLen; ++bIndex)
{
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_Rd70x_ReadRegister(
pDataParams,
PHHAL_HW_RD70X_REG_FIFO_DATA,
&pData[bIndex]));
}
*pLength = (uint16_t)bFifoLen;
return PH_ADD_COMPCODE(status, PH_COMP_HAL);
}
phStatus_t phhalHw_Rd70x_SetTypeBRegs(
phhalHw_Rd70x_DataParams_t * pDataParams
)
{
phStatus_t PH_MEMLOC_REM statusTmp;
uint8_t PH_MEMLOC_REM bRegister;
/* Retrieve ChannelRedundancy Register */
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_Rd70x_ReadRegister(
pDataParams,
PHHAL_HW_RD70X_REG_CHANNEL_REDUND,
&bRegister));
/* Set CRC for TypeB */
bRegister |= PHHAL_HW_RD70X_BIT_CRC3309;
/* Write changed ChannelRedundancy Register */
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_Rd70x_WriteRegister(
pDataParams,
PHHAL_HW_RD70X_REG_CHANNEL_REDUND,
bRegister));
/* Retrieve CoderControl Register */
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_Rd70x_ReadRegister(
pDataParams,
PHHAL_HW_RD70X_REG_CODER_CONTROL,
&bRegister));
/* Mask out current CoderRate and TxCoding settings */
bRegister &= (uint8_t)~(uint8_t)(PHHAL_HW_RD70X_MASK_CODERRATE | PHHAL_HW_RD70X_MASK_TXCODING);
/* Set TypeB settings */
bRegister |= PHHAL_HW_RD70X_BIT_TXCODING_TYPEB;
switch (pDataParams->wCfgShadow[PHHAL_HW_CONFIG_TXDATARATE])
{
case PHHAL_HW_RF_DATARATE_106:
bRegister |= PHHAL_HW_RD70X_BIT_CODERRATE_TYPEB;
break;
case PHHAL_HW_RF_DATARATE_212:
bRegister |= PHHAL_HW_RD70X_BIT_CODERRATE_106K;
break;
case PHHAL_HW_RF_DATARATE_424:
bRegister |= PHHAL_HW_RD70X_BIT_CODERRATE_212K;
break;
case PHHAL_HW_RF_DATARATE_848:
bRegister |= PHHAL_HW_RD70X_BIT_CODERRATE_424K;
break;
default:
return PH_ADD_COMPCODE(PH_ERR_INTERNAL_ERROR, PH_COMP_HAL);
}
/* Write changed CoderControl Register */
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_Rd70x_WriteRegister(
pDataParams,
PHHAL_HW_RD70X_REG_CODER_CONTROL,
bRegister));
/* Retrieve DeoderControl Register */
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_Rd70x_ReadRegister(
pDataParams,
PHHAL_HW_RD70X_REG_DECODER_CONTROL,
&bRegister));
/* Mask out current RxFraming settings */
bRegister &= (uint8_t)~(uint8_t)PHHAL_HW_RD70X_MASK_RXFRAMING;
/* Set TypeB settings */
bRegister |= PHHAL_HW_RD70X_BITS_RXFRAMING_TYPEB | PHHAL_HW_RD70X_BIT_RXCODING_BPSK;
/* Write changed DeoderControl Register */
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_Rd70x_WriteRegister(
pDataParams,
PHHAL_HW_RD70X_REG_DECODER_CONTROL,
bRegister));
/* Write BPSKDemControl Register */
bRegister = 0x0C;
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_Rd70x_WriteRegister(
pDataParams,
PHHAL_HW_RD70X_REG_BPSK_DEM_CONTROL,
bRegister));
/* Write TypeBFraming Register */
bRegister = 0x00;
PH_CHECK_SUCCESS_FCT(statusTmp, phhalHw_Rd70x_WriteRegister(
pDataParams,
PHHAL_HW_RD70X_REG_TYPEB_FRAMING,
bRegister));
return PH_ADD_COMPCODE(PH_ERR_SUCCESS, PH_COMP_HAL);
}
phStatus_t phhalHw_ReadRegister(
void * pDataParams,
uint8_t bAddress,
uint8_t * pValue
)
{
phStatus_t PH_MEMLOC_REM status;
PH_LOG_HELPER_ALLOCATE_TEXT(bFunctionName, "phhalHw_ReadRegister");
/*PH_LOG_HELPER_ALLOCATE_PARAMNAME(pDataParams);*/
PH_LOG_HELPER_ALLOCATE_PARAMNAME(bAddress);
PH_LOG_HELPER_ALLOCATE_PARAMNAME(pValue);
PH_LOG_HELPER_ALLOCATE_PARAMNAME(status);
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
PH_LOG_HELPER_ADDPARAM_UINT8(PH_LOG_LOGTYPE_DEBUG, bAddress_log, &bAddress);
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_ENTER);
PH_ASSERT_NULL (pDataParams);
PH_ASSERT_NULL (pValue);
/* Check data parameters */
if (PH_GET_COMPCODE(pDataParams) != PH_COMP_HAL)
{
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_INFO, status_log, &status);
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_LEAVE);
return PH_ADD_COMPCODE(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_HAL);
}
/* perform operation on active layer */
switch (PH_GET_COMPID(pDataParams))
{
#ifdef NXPBUILD__PHHAL_HW_RC663
case PHHAL_HW_RC663_ID:
status = phhalHw_Rc663_ReadRegister((phhalHw_Rc663_DataParams_t *)pDataParams, bAddress, pValue);
break;
#endif /* NXPBUILD__PHHAL_HW_RC663 */
#ifdef NXPBUILD__PHHAL_HW_RC523
case PHHAL_HW_RC523_ID:
status = phhalHw_Rc523_ReadRegister((phhalHw_Rc523_DataParams_t *)pDataParams, bAddress, pValue);
break;
#endif /* NXPBUILD__PHHAL_HW_RC523 */
#ifdef NXPBUILD__PHHAL_HW_RD70X
case PHHAL_HW_RD70X_ID:
status = phhalHw_Rd70x_ReadRegister((phhalHw_Rd70x_DataParams_t *)pDataParams, bAddress, pValue);
break;
#endif /* NXPBUILD__PHHAL_HW_RD70X */
#ifdef NXPBUILD__PHHAL_HW_RD710
case PHHAL_HW_RD710_ID:
status = phhalHw_Rd710_ReadRegister((phhalHw_Rd710_DataParams_t *)pDataParams, bAddress, pValue);
break;
#endif /* NXPBUILD__PHHAL_HW_RD710 */
#ifdef NXPBUILD__PHHAL_HW_CALLBACK
case PHHAL_HW_CALLBACK_ID:
status = phhalHw_Callback_ReadRegister((phhalHw_Callback_DataParams_t *)pDataParams, bAddress, pValue);
break;
#endif /* NXPBUILD__PHHAL_HW_CALLBACK */
#ifdef NXPBUILD__PHHAL_HW_RC632
case PHHAL_HW_RC632_ID:
status = phhalHw_Rc632_ReadRegister((phhalHw_Rc632_DataParams_t *)pDataParams, bAddress, pValue);
break;
#endif /* NXPBUILD__PHHAL_HW_RC632 */
default:
status = PH_ADD_COMPCODE(PH_ERR_INVALID_DATA_PARAMS, PH_COMP_HAL);
break;
}
PH_LOG_HELPER_ADDSTRING(PH_LOG_LOGTYPE_INFO, bFunctionName);
PH_LOG_HELPER_ADDPARAM_UINT8(PH_LOG_LOGTYPE_DEBUG, pValue_log, pValue);
PH_LOG_HELPER_ADDPARAM_UINT16(PH_LOG_LOGTYPE_INFO, status_log, &status);
PH_LOG_HELPER_EXECUTE(PH_LOG_OPTION_CATEGORY_LEAVE);
return status;
}
