/* Transmit DMA interrupt service */
static inline void sca_tx_intr(port_t *port)
{
struct net_device *dev = port_to_dev(port);
u16 dmac = get_dmac_tx(port);
card_t* card = port_to_card(port);
u8 stat;
spin_lock(&port->lock);
stat = sca_in(DSR_TX(phy_node(port)), card); /* read DMA Status */
/* Reset DSR status bits */
sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
DSR_TX(phy_node(port)), card);
while (1) {
pkt_desc __iomem *desc;
u32 desc_off = desc_offset(port, port->txlast, 1);
u32 cda = sca_inw(dmac + CDAL, card);
if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc)))
break; /* Transmitter is/will_be sending this frame */
desc = desc_address(port, port->txlast, 1);
dev->stats.tx_packets++;
dev->stats.tx_bytes += readw(&desc->len);
writeb(0, &desc->stat); /* Free descriptor */
port->txlast = next_desc(port, port->txlast, 1);
}
netif_wake_queue(dev);
spin_unlock(&port->lock);
}
/* Receive DMA interrupt service */
static inline void sca_rx_intr(port_t *port)
{
struct net_device *dev = port_to_dev(port);
u16 dmac = get_dmac_rx(port);
card_t *card = port_to_card(port);
u8 stat = sca_in(DSR_RX(phy_node(port)), card); /* read DMA Status */
/* Reset DSR status bits */
sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
DSR_RX(phy_node(port)), card);
if (stat & DSR_BOF)
/* Dropped one or more frames */
dev->stats.rx_over_errors++;
while (1) {
u32 desc_off = desc_offset(port, port->rxin, 0);
pkt_desc __iomem *desc;
u32 cda = sca_inw(dmac + CDAL, card);
if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc)))
break; /* No frame received */
desc = desc_address(port, port->rxin, 0);
stat = readb(&desc->stat);
if (!(stat & ST_RX_EOM))
port->rxpart = 1; /* partial frame received */
else if ((stat & ST_ERROR_MASK) || port->rxpart) {
dev->stats.rx_errors++;
if (stat & ST_RX_OVERRUN)
dev->stats.rx_fifo_errors++;
else if ((stat & (ST_RX_SHORT | ST_RX_ABORT |
ST_RX_RESBIT)) || port->rxpart)
dev->stats.rx_frame_errors++;
else if (stat & ST_RX_CRC)
dev->stats.rx_crc_errors++;
if (stat & ST_RX_EOM)
port->rxpart = 0; /* received last fragment */
} else
sca_rx(card, port, desc, port->rxin);
/* Set new error descriptor address */
sca_outw(desc_off, dmac + EDAL, card);
port->rxin = next_desc(port, port->rxin, 0);
}
/* make sure RX DMA is enabled */
sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
}
static inline void sca_rx_intr(port_t *port)
{
struct net_device *dev = port_to_dev(port);
u16 dmac = get_dmac_rx(port);
card_t *card = port_to_card(port);
u8 stat = sca_in(DSR_RX(phy_node(port)), card);
sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
DSR_RX(phy_node(port)), card);
if (stat & DSR_BOF)
dev->stats.rx_over_errors++;
while (1) {
u32 desc_off = desc_offset(port, port->rxin, 0);
pkt_desc __iomem *desc;
u32 cda = sca_inw(dmac + CDAL, card);
if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc)))
break;
desc = desc_address(port, port->rxin, 0);
stat = readb(&desc->stat);
if (!(stat & ST_RX_EOM))
port->rxpart = 1;
else if ((stat & ST_ERROR_MASK) || port->rxpart) {
dev->stats.rx_errors++;
if (stat & ST_RX_OVERRUN)
dev->stats.rx_fifo_errors++;
else if ((stat & (ST_RX_SHORT | ST_RX_ABORT |
ST_RX_RESBIT)) || port->rxpart)
dev->stats.rx_frame_errors++;
else if (stat & ST_RX_CRC)
dev->stats.rx_crc_errors++;
if (stat & ST_RX_EOM)
port->rxpart = 0;
} else
sca_rx(card, port, desc, port->rxin);
sca_outw(desc_off, dmac + EDAL, card);
port->rxin = next_desc(port, port->rxin, 0);
}
sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
}
static void pc300_set_iface(port_t *port)
{
card_t *card = port->card;
u32 __iomem * init_ctrl = &card->plxbase->init_ctrl;
u16 msci = get_msci(port);
u8 rxs = port->rxs & CLK_BRG_MASK;
u8 txs = port->txs & CLK_BRG_MASK;
sca_out(EXS_TES1, (phy_node(port) ? MSCI1_OFFSET : MSCI0_OFFSET) + EXS,
port_to_card(port));
switch(port->settings.clock_type) {
case CLOCK_INT:
rxs |= CLK_BRG; /* BRG output */
txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
break;
case CLOCK_TXINT:
rxs |= CLK_LINE; /* RXC input */
txs |= CLK_PIN_OUT | CLK_BRG; /* BRG output */
break;
case CLOCK_TXFROMRX:
rxs |= CLK_LINE; /* RXC input */
txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
break;
default: /* EXTernal clock */
rxs |= CLK_LINE; /* RXC input */
txs |= CLK_PIN_OUT | CLK_LINE; /* TXC input */
break;
}
port->rxs = rxs;
port->txs = txs;
sca_out(rxs, msci + RXS, card);
sca_out(txs, msci + TXS, card);
sca_set_port(port);
if (port->card->type == PC300_RSV) {
if (port->iface == IF_IFACE_V35)
writel(card->init_ctrl_value |
PC300_CHMEDIA_MASK(port->phy_node), init_ctrl);
else
writel(card->init_ctrl_value &
~PC300_CHMEDIA_MASK(port->phy_node), init_ctrl);
}
}
static void pci200_set_iface(port_t *port)
{
card_t *card = port->card;
u16 msci = get_msci(port);
u8 rxs = port->rxs & CLK_BRG_MASK;
u8 txs = port->txs & CLK_BRG_MASK;
sca_out(EXS_TES1, (phy_node(port) ? MSCI1_OFFSET : MSCI0_OFFSET) + EXS,
port_to_card(port));
switch(port->settings.clock_type) {
case CLOCK_INT:
rxs |= CLK_BRG; /* BRG output */
txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
break;
case CLOCK_TXINT:
rxs |= CLK_LINE; /* RXC input */
txs |= CLK_PIN_OUT | CLK_BRG; /* BRG output */
break;
case CLOCK_TXFROMRX:
rxs |= CLK_LINE; /* RXC input */
txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
break;
default: /* EXTernal clock */
rxs |= CLK_LINE; /* RXC input */
txs |= CLK_PIN_OUT | CLK_LINE; /* TXC input */
break;
}
port->rxs = rxs;
port->txs = txs;
sca_out(rxs, msci + RXS, card);
sca_out(txs, msci + TXS, card);
sca_set_port(port);
}
static void sca_init_port(port_t *port)
{
card_t *card = port_to_card(port);
int transmit, i;
port->rxin = 0;
port->txin = 0;
port->txlast = 0;
#ifndef PAGE0_ALWAYS_MAPPED
openwin(card, 0);
#endif
for (transmit = 0; transmit < 2; transmit++) {
u16 dmac = transmit ? get_dmac_tx(port) : get_dmac_rx(port);
u16 buffs = transmit ? card->tx_ring_buffers
: card->rx_ring_buffers;
for (i = 0; i < buffs; i++) {
pkt_desc __iomem *desc = desc_address(port, i, transmit);
u16 chain_off = desc_offset(port, i + 1, transmit);
u32 buff_off = buffer_offset(port, i, transmit);
writew(chain_off, &desc->cp);
writel(buff_off, &desc->bp);
writew(0, &desc->len);
writeb(0, &desc->stat);
}
/* DMA disable - to halt state */
sca_out(0, transmit ? DSR_TX(phy_node(port)) :
DSR_RX(phy_node(port)), card);
/* software ABORT - to initial state */
sca_out(DCR_ABORT, transmit ? DCR_TX(phy_node(port)) :
DCR_RX(phy_node(port)), card);
/* current desc addr */
sca_out(0, dmac + CPB, card); /* pointer base */
sca_outw(desc_offset(port, 0, transmit), dmac + CDAL, card);
if (!transmit)
sca_outw(desc_offset(port, buffs - 1, transmit),
dmac + EDAL, card);
else
sca_outw(desc_offset(port, 0, transmit), dmac + EDAL,
card);
/* clear frame end interrupt counter */
sca_out(DCR_CLEAR_EOF, transmit ? DCR_TX(phy_node(port)) :
DCR_RX(phy_node(port)), card);
if (!transmit) { /* Receive */
/* set buffer length */
sca_outw(HDLC_MAX_MRU, dmac + BFLL, card);
/* Chain mode, Multi-frame */
sca_out(0x14, DMR_RX(phy_node(port)), card);
sca_out(DIR_EOME | DIR_BOFE, DIR_RX(phy_node(port)),
card);
/* DMA enable */
sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
} else { /* Transmit */
/* Chain mode, Multi-frame */
sca_out(0x14, DMR_TX(phy_node(port)), card);
/* enable underflow interrupts */
sca_out(DIR_BOFE, DIR_TX(phy_node(port)), card);
}
}
sca_set_carrier(port);
}
static void sca_init_port(port_t *port)
{
card_t *card = port_to_card(port);
int transmit, i;
port->rxin = 0;
port->txin = 0;
port->txlast = 0;
#ifndef PAGE0_ALWAYS_MAPPED
openwin(card, 0);
#endif
for (transmit = 0; transmit < 2; transmit++) {
u16 dmac = transmit ? get_dmac_tx(port) : get_dmac_rx(port);
u16 buffs = transmit ? card->tx_ring_buffers
: card->rx_ring_buffers;
for (i = 0; i < buffs; i++) {
pkt_desc __iomem *desc = desc_address(port, i, transmit);
u16 chain_off = desc_offset(port, i + 1, transmit);
u32 buff_off = buffer_offset(port, i, transmit);
writew(chain_off, &desc->cp);
writel(buff_off, &desc->bp);
writew(0, &desc->len);
writeb(0, &desc->stat);
}
sca_out(0, transmit ? DSR_TX(phy_node(port)) :
DSR_RX(phy_node(port)), card);
sca_out(DCR_ABORT, transmit ? DCR_TX(phy_node(port)) :
DCR_RX(phy_node(port)), card);
sca_out(0, dmac + CPB, card);
sca_outw(desc_offset(port, 0, transmit), dmac + CDAL, card);
if (!transmit)
sca_outw(desc_offset(port, buffs - 1, transmit),
dmac + EDAL, card);
else
sca_outw(desc_offset(port, 0, transmit), dmac + EDAL,
card);
sca_out(DCR_CLEAR_EOF, transmit ? DCR_TX(phy_node(port)) :
DCR_RX(phy_node(port)), card);
if (!transmit) {
sca_outw(HDLC_MAX_MRU, dmac + BFLL, card);
sca_out(0x14, DMR_RX(phy_node(port)), card);
sca_out(DIR_EOME | DIR_BOFE, DIR_RX(phy_node(port)),
card);
sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
} else {
sca_out(0x14, DMR_TX(phy_node(port)), card);
sca_out(DIR_BOFE, DIR_TX(phy_node(port)), card);
}
}
sca_set_carrier(port);
}
