void
init_hwinfo()
{
/* start the on-chip PHY and its PLL */
phy_on(AM335X_USBCTRL0);
usb_delay(5);
phy_on(AM335X_USBCTRL1);
usb_delay(5);
/* Force enable of CLKDCOLDO clock */
out32(AM335X_CM_CLKDCOLDO_DPLL_PER, DPLL_CLKDCOLDO_GATE_CTRL);
}
/*
* This function performs Davinci platform specific initialization for usb0.
*/
int musb_platform_init(void)
{
u32 revision;
/* enable USB VBUS */
enable_vbus();
/* start the on-chip USB phy and its pll */
if (!phy_on())
return -1;
/* reset the controller */
dregs = (struct davinci_usb_regs *)DAVINCI_USB0_BASE;
writel(1, &dregs->ctrlr);
udelay(5000);
/* Returns zero if e.g. not clocked */
revision = readl(&dregs->version);
if (!revision)
return -1;
/* Disable all interrupts */
writel(DAVINCI_USB_USBINT_MASK | DAVINCI_USB_RXINT_MASK |
DAVINCI_USB_TXINT_MASK , &dregs->intmsksetr);
return 0;
}
/*
* This function performs DA8xx platform specific initialization for usb0.
*/
int musb_platform_init(void)
{
u32 revision;
/* enable psc for usb2.0 */
lpsc_on(33);
/* enable usb vbus */
enable_vbus();
/* reset the controller */
writel(0x1, &da8xx_usb_regs->control);
udelay(5000);
/* start the on-chip usb phy and its pll */
if (phy_on() == 0)
return -1;
/* Returns zero if e.g. not clocked */
revision = readl(&da8xx_usb_regs->revision);
if (revision == 0)
return -1;
/* Disable all interrupts */
writel((DA8XX_USB_USBINT_MASK | DA8XX_USB_TXINT_MASK |
DA8XX_USB_RXINT_MASK), &da8xx_usb_regs->intmsk_set);
return 0;
}
int __init musb_platform_init(struct musb *musb)
{
struct otg_transceiver xceiv;
void __iomem *tibase = musb->ctrl_base;
u32 revision;
musb->mregs += DAVINCI_BASE_OFFSET;
#if 0
/* REVISIT there's something odd about clocking, this
* didn't appear do the job ...
*/
musb->clock = clk_get(pDevice, "usb");
if (IS_ERR(musb->clock))
return PTR_ERR(musb->clock);
status = clk_enable(musb->clock);
if (status < 0)
return -ENODEV;
#endif
memset(&xceiv, 0, sizeof(xceiv));
xceiv.label = "davinci";
xceiv.dev = musb->controller;
otg_set_transceiver(&xceiv);
musb->xceiv = &xceiv;
/* returns zero if e.g. not clocked */
revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
if (revision == 0)
return -ENODEV;
if (is_host_enabled(musb))
setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
musb->board_set_vbus = davinci_set_vbus;
davinci_source_power(musb, 0, 1);
/* reset the controller */
musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);
/* start the on-chip PHY and its PLL */
phy_on();
msleep(5);
/* NOTE: irqs are in mixed mode, not bypass to pure-musb */
pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
revision, __raw_readl((void __force __iomem *)
IO_ADDRESS(USBPHY_CTL_PADDR)),
musb_readb(tibase, DAVINCI_USB_CTRL_REG));
musb->isr = davinci_interrupt;
musb->suspendm = true;
return 0;
}
/*
* This function performs platform specific initialization for usb0.
*/
int musb_platform_init(void)
{
if (!phy_on()) {
printf("phy_on failed");
return -1;
}
regs = (struct am335x_usb_regs *)MUSB_BASE;
/* Enable the IRQ on USB0 wrapper register instead of MUSB register */
writel(USB_IRQENABLE_SET, ®s->irq_enableset0);
return 0;
}
static int da8xx_musb_init(struct musb *musb)
{
void __iomem *reg_base = musb->ctrl_base;
u32 rev;
int ret = -ENODEV;
musb->mregs += DA8XX_MENTOR_CORE_OFFSET;
/* Returns zero if e.g. not clocked */
rev = musb_readl(reg_base, DA8XX_USB_REVISION_REG);
if (!rev)
goto fail;
usb_nop_xceiv_register();
musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
if (IS_ERR_OR_NULL(musb->xceiv)) {
ret = -EPROBE_DEFER;
goto fail;
}
setup_timer(&otg_workaround, otg_timer, (unsigned long)musb);
/* Reset the controller */
musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK);
/* Start the on-chip PHY and its PLL. */
phy_on();
msleep(5);
/* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */
pr_debug("DA8xx OTG revision %08x, PHY %03x, control %02x\n",
rev, __raw_readl(CFGCHIP2),
musb_readb(reg_base, DA8XX_USB_CTRL_REG));
musb->isr = da8xx_musb_interrupt;
return 0;
fail:
return ret;
}
int __init musb_platform_init(struct musb *musb)
{
void __iomem *tibase = musb->ctrl_base;
u32 revision;
musb->mregs += DAVINCI_BASE_OFFSET;
clk_enable(musb->clock);
/* returns zero if e.g. not clocked */
revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
if (revision == 0)
return -ENODEV;
if (is_host_enabled(musb))
setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
musb->board_set_vbus = davinci_set_vbus;
davinci_source_power(musb, 0, 1);
/* reset the controller */
musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);
/* start the on-chip PHY and its PLL */
phy_on();
msleep(5);
/* NOTE: irqs are in mixed mode, not bypass to pure-musb */
pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
revision, __raw_readl((void __force __iomem *)
IO_ADDRESS(USBPHY_CTL_PADDR)),
musb_readb(tibase, DAVINCI_USB_CTRL_REG));
musb->isr = davinci_interrupt;
return 0;
}
static int davinci_musb_init(struct musb *musb)
{
void __iomem *tibase = musb->ctrl_base;
u32 revision;
int ret = -ENODEV;
usb_nop_xceiv_register();
musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
if (IS_ERR_OR_NULL(musb->xceiv)) {
ret = -EPROBE_DEFER;
goto unregister;
}
musb->mregs += DAVINCI_BASE_OFFSET;
/* returns zero if e.g. not clocked */
revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
if (revision == 0)
goto fail;
setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
davinci_musb_source_power(musb, 0, 1);
/* dm355 EVM swaps D+/D- for signal integrity, and
* is clocked from the main 24 MHz crystal.
*/
if (machine_is_davinci_dm355_evm()) {
u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
phy_ctrl &= ~(3 << 9);
phy_ctrl |= USBPHY_DATAPOL;
__raw_writel(phy_ctrl, USB_PHY_CTRL);
}
/* On dm355, the default-A state machine needs DRVVBUS control.
* If we won't be a host, there's no need to turn it on.
*/
if (cpu_is_davinci_dm355()) {
u32 deepsleep = __raw_readl(DM355_DEEPSLEEP);
deepsleep &= ~DRVVBUS_FORCE;
__raw_writel(deepsleep, DM355_DEEPSLEEP);
}
/* reset the controller */
musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);
/* start the on-chip PHY and its PLL */
phy_on();
msleep(5);
/* NOTE: irqs are in mixed mode, not bypass to pure-musb */
pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
revision, __raw_readl(USB_PHY_CTRL),
musb_readb(tibase, DAVINCI_USB_CTRL_REG));
musb->isr = davinci_musb_interrupt;
return 0;
fail:
usb_put_phy(musb->xceiv);
unregister:
usb_nop_xceiv_unregister();
return ret;
}
int __init musb_platform_init(struct musb *musb)
{
void __iomem *tibase = musb->ctrl_base;
u32 revision;
usb_nop_xceiv_register();
musb->xceiv = otg_get_transceiver();
if (!musb->xceiv)
return -ENODEV;
musb->mregs += DAVINCI_BASE_OFFSET;
clk_enable(musb->clock);
/* returns zero if e.g. not clocked */
revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
if (revision == 0)
goto fail;
if (is_host_enabled(musb))
setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
musb->board_set_vbus = davinci_set_vbus;
davinci_source_power(musb, 0, 1);
/* dm355 EVM swaps D+/D- for signal integrity, and
* is clocked from the main 24 MHz crystal.
*/
if (machine_is_davinci_dm355_evm()) {
u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
phy_ctrl &= ~(3 << 9);
phy_ctrl |= USBPHY_DATAPOL;
__raw_writel(phy_ctrl, USB_PHY_CTRL);
}
/* On dm355, the default-A state machine needs DRVVBUS control.
* If we won't be a host, there's no need to turn it on.
*/
if (cpu_is_davinci_dm355()) {
u32 deepsleep = __raw_readl(DM355_DEEPSLEEP);
if (is_host_enabled(musb)) {
deepsleep &= ~DRVVBUS_OVERRIDE;
} else {
deepsleep &= ~DRVVBUS_FORCE;
deepsleep |= DRVVBUS_OVERRIDE;
}
__raw_writel(deepsleep, DM355_DEEPSLEEP);
}
/* reset the controller */
musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);
/* start the on-chip PHY and its PLL */
phy_on();
msleep(5);
/* NOTE: irqs are in mixed mode, not bypass to pure-musb */
pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
revision, __raw_readl(USB_PHY_CTRL),
musb_readb(tibase, DAVINCI_USB_CTRL_REG));
musb->isr = davinci_interrupt;
return 0;
fail:
usb_nop_xceiv_unregister();
return -ENODEV;
}
static int davinci_musb_init(struct musb *musb)
{
void __iomem *tibase = musb->ctrl_base;
u32 revision;
usb_nop_xceiv_register();
musb->xceiv = usb_get_transceiver();
if (!musb->xceiv)
goto unregister;
musb->mregs += DAVINCI_BASE_OFFSET;
revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
if (revision == 0)
goto fail;
if (is_host_enabled(musb))
setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
davinci_musb_source_power(musb, 0, 1);
if (machine_is_davinci_dm355_evm()) {
u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
phy_ctrl &= ~(3 << 9);
phy_ctrl |= USBPHY_DATAPOL;
__raw_writel(phy_ctrl, USB_PHY_CTRL);
}
if (cpu_is_davinci_dm355()) {
u32 deepsleep = __raw_readl(DM355_DEEPSLEEP);
if (is_host_enabled(musb)) {
deepsleep &= ~DRVVBUS_OVERRIDE;
} else {
deepsleep &= ~DRVVBUS_FORCE;
deepsleep |= DRVVBUS_OVERRIDE;
}
__raw_writel(deepsleep, DM355_DEEPSLEEP);
}
musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);
phy_on();
msleep(5);
pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
revision, __raw_readl(USB_PHY_CTRL),
musb_readb(tibase, DAVINCI_USB_CTRL_REG));
musb->isr = davinci_musb_interrupt;
return 0;
fail:
usb_put_transceiver(musb->xceiv);
unregister:
usb_nop_xceiv_unregister();
return -ENODEV;
}
int __init musb_platform_init(struct musb *musb)
{
void *__iomem tibase = musb->ctrl_base;
u32 revision, phystatus;
u8 id;
struct platform_device *pdev = to_platform_device(musb->controller);
struct musb_hdrc_platform_data *plat;
struct clk *clkp;
if (pdev->id == -1)
id = 0;
else
id = pdev->id;
switch (id) {
case 0 :
clkp = clk_get (NULL, "USBCLK");
break;
default :
return -ENODEV;
}
if (IS_ERR(clkp))
return -ENODEV;
musb->clock = clkp;
clk_use (clkp);
if (clk_enable (clkp) != 0)
return -ENODEV;
plat = musb->controller->platform_data;
/* overwrite the USB mode */
#ifdef CONFIG_USB_MUSB_HDRC_HCD
plat->mode = MUSB_HOST;
#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
plat->mode = MUSB_PERIPHERAL;
#elif defined(CONFIG_USB_MUSB_OTG)
plat->mode = MUSB_OTG;
#else
dev_dbg(musb->controller, "incompatible Kconfig role setting");
return -EINVAL;
#endif
musb->board_mode = plat->mode;
musb->pRegs += DAVINCI_BASE_OFFSET;
/* returns zero if e.g. not clocked */
revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
if (revision == 0)
return -ENODEV;
/* note that transceiver issues make us want to charge
* VBUS only when the PHY PLL is not active.
*/
#if defined(CONFIG_MACH_DAVINCI_EVM) || defined (CONFIG_MACH_DAVINCI_HD_EVM)
#ifdef CONFIG_USB_MUSB_OTG
/* clear EMACEN to enble OTG GPIO 16 for VBus power control */
/* Set GPIO Direction */
REG_DVEVM_GPIO45_DIR &= ~(DVEVM_GPIO45_DIR_OUT);
davinci_cfg_reg(DM644X_GPIO3V);
#endif
evm_vbus_work.data = musb;
#endif
#ifdef CONFIG_ARCH_DAVINCI_DM355
#ifdef CONFIG_USB_MUSB_HDRC_HCD
gpio_direction_output(2, 1);
#else
gpio_direction_output(2, 0);
#endif
__raw_writel( __raw_readl (IO_ADDRESS(DM355_DEEPSLEEP_REG)) &
0xfffffff0, IO_ADDRESS (DM355_DEEPSLEEP_REG));
#endif
/* reset the controller */
musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);
/* start the on-chip PHY and its PLL */
phy_on();
msleep(5);
phystatus = __raw_readl(IO_ADDRESS(USBPHY_CTL_PADDR));
#ifdef CONFIG_ARCH_DAVINCI_DM646x
#ifdef CONFIG_USB_MUSB_HDRC_HCD
__raw_writel(phystatus | DM646X_USBPHY_SESSION_VBUS |
DM646X_USBPHY_NDATAPOL, IO_ADDRESS(USBPHY_CTL_PADDR));
#else
__raw_writel (phystatus | DM646X_USBPHY_SESSION_VBUS |
DM646X_USBPHY_NDATAPOL | DM646X_USBPHY_PERI_USBID,
IO_ADDRESS(USBPHY_CTL_PADDR));
#endif
#endif
/* NOTE: irqs are in mixed mode, not bypass to pure-musb */
pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
revision,
musb_readl((void *__iomem)IO_ADDRESS(USBPHY_CTL_PADDR), 0x00),
musb_readb(tibase, DAVINCI_USB_CTRL_REG));
musb->isr = davinci_interrupt;
return 0;
}
int __init musb_platform_init(struct musb *musb)
{
void *__iomem tibase = musb->ctrl_base;
u32 revision, phystatus;
#ifdef CONFIG_ARCH_DAVINCI
struct clk *clkp;
clkp = clk_get (NULL, "USBCLK");
if (IS_ERR(clkp))
return -ENODEV;
musb->clock = clkp;
clk_use (clkp);
if(clk_enable (clkp) != 0)
return -ENODEV;
#endif
musb->pRegs += DAVINCI_BASE_OFFSET;
/* returns zero if e.g. not clocked */
revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
if (revision == 0)
return -ENODEV;
/* note that transceiver issues make us want to charge
* VBUS only when the PHY PLL is not active.
*/
#if defined(CONFIG_MACH_DAVINCI_EVM) || defined (CONFIG_MACH_DAVINCI_HD_EVM)
#ifdef CONFIG_USB_MUSB_OTG
/* clear EMACEN to enble OTG GPIO 16 for VBus power control */
/* Set GPIO Direction */
REG_DVEVM_GPIO45_DIR &= ~(DVEVM_GPIO45_DIR_OUT);
DAVINCI_PINMUX0 &= ~(0x80000000);
#endif
evm_vbus_work.data = musb;
#endif
#ifdef CONFIG_ARCH_DAVINCI355
gpio_set_direction(2, GIO_DIR_OUTPUT);
#ifdef CONFIG_USB_MUSB_HDRC_HCD
__gpio_set(2, 1);
#else
__gpio_set(2, 0);
#endif
__raw_writel( __raw_readl(IO_ADDRESS(DEEPSLEEP_REG)) & 0xfffffff0,
IO_ADDRESS(DEEPSLEEP_REG));
#endif
/* reset the controller */
musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);
phy_on();
msleep(5);
phystatus = __raw_readl(IO_ADDRESS(USBPHY_CTL_PADDR));
#ifdef CONFIG_ARCH_DAVINCI646x
#ifdef CONFIG_USB_MUSB_HDRC_HCD
__raw_writel(phystatus | USBPHY_SESSION_VBUS | USBPHY_NDATAPOL,
IO_ADDRESS(USBPHY_CTL_PADDR));
#else
__raw_writel (phystatus | USBPHY_SESSION_VBUS | USBPHY_NDATAPOL |
USBPHY_PERI_USBID, IO_ADDRESS(USBPHY_CTL_PADDR));
#endif
#endif
/* NOTE: irqs are in mixed mode, not bypass to pure-musb */
pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
revision,
musb_readl((void *__iomem)IO_ADDRESS(USBPHY_CTL_PADDR), 0x00),
musb_readb(tibase, DAVINCI_USB_CTRL_REG));
musb->isr = davinci_interrupt;
return 0;
}