int __init arch_defterm_init(void)
{
pba8_defterm_base = vmm_host_iomap(PBA8_DEFAULT_UART_BASE, 0x1000);
pl011_lowlevel_init(pba8_defterm_base,
PBA8_DEFAULT_UART_BAUD, PBA8_DEFAULT_UART_INCLK);
return VMM_OK;
}
int __init arch_defterm_init(void)
{
int rc;
u32 *val;
struct vmm_devtree_node *node;
node = vmm_devtree_getnode(VMM_DEVTREE_PATH_SEPARATOR_STRING
VMM_DEVTREE_HOSTINFO_NODE_NAME
VMM_DEVTREE_PATH_SEPARATOR_STRING "motherboard"
VMM_DEVTREE_PATH_SEPARATOR_STRING "iofpga"
VMM_DEVTREE_PATH_SEPARATOR_STRING "uart0");
if (!node) {
return VMM_ENODEV;
}
rc = vmm_devtree_regmap(node, &v2m_defterm_base, 0);
if (rc) {
return rc;
}
val = vmm_devtree_attrval(node, VMM_DEVTREE_CLOCK_RATE_ATTR_NAME);
v2m_defterm_inclk = (val) ? *val : 24000000;
val = vmm_devtree_attrval(node, "baudrate");
v2m_defterm_baud = (val) ? *val : 115200;
pl011_lowlevel_init(v2m_defterm_base,
v2m_defterm_baud,
v2m_defterm_inclk);
return VMM_OK;
}
static int __init pl011_defterm_init(struct vmm_devtree_node *node)
{
int rc;
rc = vmm_devtree_regmap(node, &pl011_defterm_base, 0);
if (rc) {
return rc;
}
rc = vmm_devtree_clock_frequency(node,
&pl011_defterm_inclk);
if (rc) {
return rc;
}
if (vmm_devtree_read_u32(node, "baudrate",
&pl011_defterm_baud)) {
pl011_defterm_baud = 115200;
}
pl011_lowlevel_init(pl011_defterm_base,
pl011_defterm_baud,
pl011_defterm_inclk);
return VMM_OK;
}
