/**
* @brief
* Configure the sgmii Serdes on devices using the initialization sequence
*/
void configSerdes()
{
/* Unlock the chip configuration registers to allow SGMII SERDES registers to
* be written */
CSL_BootCfgUnlockKicker();
/* Configure the SERDES */
/* Multiply to be 8 with Quarter Rate in the Rx registers */
CSL_BootCfgSetSGMIIConfigPLL (0x00000041);
platform_delaycycles(100);
//31:25 Reserved 0000000
//23:24 LOOPBACK 00
// 22 ENOC 1
//21:18 EQ 0001
//17:15 CDR 001 -- first order threshold of 17
//14:12 LOS 000 -- tie off
//11:10 ALIGN 01 -- Comma Aligned
//09:07 TERM 100 -- tie off (100)
// 06 INVPAIR 0
//05:04 RATE 01 -- tie off (10) //00 = Full Rate, 01 = Half Rate (*0.5), 10 = Quarter Rate (*0.25)
//03:01 BUSWIDTH 000 -- tie off
// 00 ENRX 1
// 0000 0000 0100 0100 0000 0010 0001 0001 = 0x0044_0211 -- My estimated value
// 0000 0000 0100 0100 0000 0100 0001 0001 = 0x0044_0411 -- New DV value
// 0000 0000 0000 1000 0000 1000 0100 0001 = 0x0008_0841 -- Original DV value
CSL_BootCfgSetSGMIIRxConfig (0, 0x00700621);
CSL_BootCfgSetSGMIIRxConfig (1, 0x00700621);
//31:22 Reserved 0
//21:20 LOOPBACK 00
//19:18 RDTCT 00 -- tie off
// 17 ENIDL 0 -- tie off
// 16 MYSNC 1 -- tie off
//15:12 DEMPHASIS ???? - 0001 Lets give some de-emphasis
//11:08 SWING ????
// 07 CM 1 -- tie off
// 06 INVPAIR 0
//05:04 RATE 01 -- tie off
//03:01 BUSWIDTH 000 -- tie off
// 00 ENTX 1
// 0000 0000 0011 0001 ???? ???? 1001 0001 = 0x0031_1E91 -- My estimated value
// 0000 0000 0000 0001 0000 1111 0001 0001 = 0x0001_0F11 -- New DV value
// 0000 0000 0100 0000 0001 1110 0100 0001 = 0x0040_1e41 -- Original DV value
CSL_BootCfgSetSGMIITxConfig (0, 0x000108A1);
CSL_BootCfgSetSGMIITxConfig (1, 0x000108A1);
/* All done with configuration. Return Now. */
return;
}
float acquire_data()
{
//GPIO_3-CNVST, GPIO_13-CS
//Start the ADC communication
timer_flag=0;
//Timer_start(timer1);
platform_write("stated timer \n");
data_index=0;
int cnt=0;
long int tscl_val, tsch_val;
long int tscl_val1, tsch_val1;
float elapsed_time=0;
for(;;)
{
TSCL = 0;
TSCH = 0;
tscl_val = TSCL;
//tsch_val = TSCH;
/*if(timer_flag==1)
{
platform_write("processing sample %d \n",cnt);
timer_flag=0;
break;
}*/
//Pull CNVST low
//platform_write("eeee");
gpioClearOutput(GPIO_3);
//platform_write("BBBB");
//Wait for 50ns right now without any delay (10ns minimum)
//Set CNVST high again
gpioSetOutput(GPIO_3);
//platform_write("CCCCC");
platform_delaycycles(650); //Approximately 650 ns for 500 argument and 720ns for 600 argument
//Pull CS pin low
gpioClearOutput(GPIO_13);
//platform_write("DDDDD");
//gpioSetOutput(GPIO_7);
for(i=0; i<28; i++)
{
gpioClearOutput(GPIO_7);
if(i==0 || i==14)
{
if(i==0)
data_bufferA[data_index]=0;
else if(i==14)
data_bufferB[data_index]=0;
platform_delaycycles(100);
//platform_write("AAAA");
data_bit=gpioReadInput(GPIO_10);
//platform_write("FFFFF");
}
else
platform_delaycycles(60);
if(i<14)
data_bufferA[data_index]=(data_bufferA[data_index]<<1)+data_bit;
if(i<28 && i >=14)
data_bufferB[data_index]=(data_bufferB[data_index]<<1)+data_bit;
gpioSetOutput(GPIO_7);
interrupt_call_count=0;
if(i==27)
{
if(data_bufferB[data_index]>NEGATIVE_VALUE_MARGIN) //Means negative value
data_bufferB[data_index] = data_bufferB[data_index]-FULL_SCALE_VALUE; //Invert the value
}
if(i==13)
{
if(data_bufferA[data_index]>NEGATIVE_VALUE_MARGIN) //Means negative value
data_bufferA[data_index] = data_bufferB[data_index]-FULL_SCALE_VALUE; //Invert the value
}
}
//Release CS pin
gpioSetOutput(GPIO_13);
cnt++;
data_index=data_index+1;
data_index=data_index%PULSE_SAMPLE;
tscl_val1 = TSCL;
elapsed_time += ((float)(tscl_val1-tscl_val)/(float)DSP_clockcycles_persec);//_itoll(tsch_val, tscl_val);
if(elapsed_time >=2 )
break;
//platform_write("elapsed time for sample is %d ",elapsed_time);
// if(data_index==0)
// break;
}
platform_write("Total number of samples are %d,%f \n",cnt,elapsed_time);
return cnt;
}
