// a-timer11 0x90004xxx c-timer20 0x90004050
OSL_IRQ_FUNC(irqreturn_t, timer11_irq, intLvl, dev)
{
u32 ret = 0;
u32 t11_addr = HI_TIMER_11_REGBASE_ADDR_VIRT;
ret = readl(t11_addr+HI_TIMER_EOI_OFFSET); /*clear int*/
pm_printk(BSP_LOG_LEVEL_ERROR,"acore timer11 irq handled : 0x%x \n",ret);
return IRQ_HANDLED;
}
OSL_IRQ_FUNC(irqreturn_t, timer20_irq, intLvl, dev)
{
u32 ret = 0;
u32 t20_addr = HI_TIMER_20_REGBASE_ADDR_VIRT;
ret = readl(t20_addr+HI_TIMER_EOI_OFFSET);
pm_printk(BSP_LOG_LEVEL_ERROR,"ccore timer20 irq handled : 0x%x \n",ret);
return IRQ_HANDLED;
}
/*
* hi6930_pm_disable_l2x0()/hi6930_pm_enable_l2x0() is designed to
* disable and enable l2-cache during Suspend-Resume phase
*/
void hi6930_pm_disable_l2x0(void)
{
u32 l2x0_base = HI_APPA9_L2_REGBASE_ADDR_VIRT;
/* backup aux control register value */
l2x0_cache_bak[0] = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
l2x0_cache_bak[1] = readl_relaxed(l2x0_base + L2X0_TAG_LATENCY_CTRL);
l2x0_cache_bak[2] = readl_relaxed(l2x0_base + L2X0_DATA_LATENCY_CTRL);
outer_disable();
pm_printk(BSP_LOG_LEVEL_DEBUG, "l2x0 Cache disabled.\r\n");
}
/* print clk/mtcmos status saved */
void pm_print_clk_mtcmos_status(void)
{
pm_printk(BSP_LOG_LEVEL_ERROR,"CHECK_STATUS_START =0x%x \n", CHECK_STATUS_START);
pm_printk(BSP_LOG_LEVEL_ERROR,"CHECK_CRG_CLKSTAT1 =0x%x \n", *(u32*)CHECK_CRG_CLKSTAT1);
pm_printk(BSP_LOG_LEVEL_ERROR,"CHECK_CRG_CLKSTAT2 =0x%x \n", *(u32*)CHECK_CRG_CLKSTAT2);
pm_printk(BSP_LOG_LEVEL_ERROR,"CHECK_CRG_CLKSTAT3 =0x%x \n", *(u32*)CHECK_CRG_CLKSTAT3);
pm_printk(BSP_LOG_LEVEL_ERROR,"CHECK_CRG_CLKSTAT4 =0x%x \n", *(u32*)CHECK_CRG_CLKSTAT4);
pm_printk(BSP_LOG_LEVEL_ERROR,"CHECK_CRG_CLKSTAT5 =0x%x \n", *(u32*)CHECK_CRG_CLKSTAT5);
pm_printk(BSP_LOG_LEVEL_ERROR,"CHECK_PWR_STAT1 =0x%x \n", *(u32*)CHECK_PWR_STAT1);
}
static int balong_pm_valid_state(suspend_state_t state)
{
pm_printk(BSP_LOG_LEVEL_INFO,">>>>>>>enter valid state %d<<<<<<<\n", state);
switch (state){
case PM_SUSPEND_ON:
case PM_SUSPEND_STANDBY:
case PM_SUSPEND_MEM:
return 1;
default:
return 0;
}
}
void hi6930_pm_enable_l2x0(void)
{
u32 l2x0_base = HI_APPA9_L2_REGBASE_ADDR_VIRT;
/* disable cache */
writel_relaxed(0, l2x0_base + L2X0_CTRL);
/* restore aux control register */
writel_relaxed(l2x0_cache_bak[0], l2x0_base + L2X0_AUX_CTRL);
writel_relaxed(l2x0_cache_bak[1], l2x0_base + L2X0_TAG_LATENCY_CTRL);
writel_relaxed(l2x0_cache_bak[2], l2x0_base + L2X0_DATA_LATENCY_CTRL);
/* invalidate l2x0 cache */
outer_inv_all();
/* enable l2x0 cache */
writel_relaxed(1, l2x0_base + L2X0_CTRL);
mb();
pm_printk(BSP_LOG_LEVEL_DEBUG, "L2 Cache enabled\r\n");
}
int timer_wsrc_test_init(u32 sec)
{
u32 t20_addr = HI_TIMER_20_REGBASE_ADDR_VIRT;
if(timer_irq_requested)
{
free_irq( INT_LVL_TIMER20 , 0);
}
/* 初始值 */
*(u32*)(t20_addr+HI_TIMER_LOADCOUNT_OFFSET) = HI_TIMER20_CLK*sec;
/* config */
*(u32*)(t20_addr+HI_TIMER_CONTROLREG_OFFSET) = 3;
if(request_irq(INT_LVL_TIMER20, (irq_handler_t)timer20_irq, 0, "timer20", 0))
{
pm_printk(BSP_LOG_LEVEL_ERROR, "request_irq INT_LVL_TIMER20 - FAILED! \n");
return -1;
}
timer_irq_requested = 1;
return 0;
}
void pm_set_trace_level(u32 level)
{
(void)bsp_mod_level_set(BSP_MODU_PM, level);
pm_printk(BSP_LOG_LEVEL_ERROR,"bsp_mod_level_set(BSP_MODU_PM=%d, %d)\n",BSP_MODU_PM,level);
}
