void pmic_init(unsigned bus)
{
/*
* Don't need to set up VDD_CORE - already done - by OTP
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
*/
/* Restore PMIC POR defaults, in case kernel changed 'em */
pmic_slam_defaults(bus);
/* First set VDD_CPU to 1.2V, then enable the VDD_CPU regulator. */
if (board_id() == 0)
pmic_write_reg(bus, 0x00, 0x3c, 1);
else
pmic_write_reg(bus, 0x00, 0x50, 1);
/* First set VDD_GPU to 1.0V, then enable the VDD_GPU regulator. */
pmic_write_reg(bus, 0x06, 0x28, 1);
/*
* First set +1.2V_GEN_AVDD to 1.2V, then enable the +1.2V_GEN_AVDD
* regulator.
*/
pmic_write_reg(bus, 0x12, 0x10, 1);
/*
* Panel power GPIO O4. Set mode for GPIO4 (0x0c to 7), then set
* the value (register 0x20 bit 4)
*/
pmic_write_reg(bus, 0x0c, 0x07, 0);
pmic_write_reg(bus, 0x20, 0x10, 1);
}
void pmic_init(unsigned bus)
{
/* Restore PMIC POR defaults, in case kernel changed 'em */
pmic_slam_defaults(bus);
/* A44: Set VDD_CPU to 1.0V. */
pmic_write_reg(bus, TI65913_SMPS12_VOLTAGE, 0x38, 0);
pmic_write_reg(bus, TI65913_SMPS12_CTRL, 0x01, 1);
printk(BIOS_DEBUG, "PMIC init done\n");
}
void pmic_init(unsigned bus)
{
/* Restore PMIC POR defaults, in case kernel changed 'em */
pmic_slam_defaults(bus);
/* MAX77620: Set SD0 to 1.0V - VDD_CORE */
pmic_write_reg_77620(bus, MAX77620_SD0_REG, 0x20, 1);
pmic_write_reg_77620(bus, MAX77620_VDVSSD0_REG, 0x20, 1);
/* MAX77620: GPIO 0,1,2,5,6,7 = GPIO, 3,4 = alt mode */
pmic_write_reg_77620(bus, MAX77620_AME_GPIO, 0x18, 1);
/* MAX77620: Disable SD1 Remote Sense, Set SD1 for LPDDR4 to 1.125V */
pmic_write_reg_77620(bus, MAX77620_CNFG2SD_REG, 0x04, 1);
pmic_write_reg_77620(bus, MAX77620_SD1_REG, 0x2a, 1);
/*
* MAX77620: Set LDO2 output to 1.8V. LDO2 is used as always-on
* reference for the droop alert circuit. Match this setting with what
* the kernel expects.
*/
pmic_write_reg_77620(bus, MAX77620_CNFG1_L2_REG, 0x14, 1);
/* MAX77621: Set VOUT_REG to 1.0V - CPU VREG */
pmic_write_reg_77621(bus, MAX77621_VOUT_REG, 0xBF, 1);
/* MAX77621: Set VOUT_DVC_REG to 1.0V - CPU VREG DVC */
pmic_write_reg_77621(bus, MAX77621_VOUT_DVC_REG, 0xBF, 1);
/* MAX77621: Set CONTROL1 to 0x38 */
pmic_write_reg_77621(bus, MAX77621_CONTROL1_REG, 0x38, 1);
/* MAX77621: Set CONTROL2 to 0xD2 */
pmic_write_reg_77621(bus, MAX77621_CONTROL2_REG, 0xD2, 1);
/* MAX77620: Setup/Enable GPIO5 - EN_VDD_CPU */
pmic_write_reg_77620(bus, MAX77620_GPIO5_REG, 0x09, 1);
/* Required delay of 2msec */
udelay(2000);
printk(BIOS_DEBUG, "PMIC init done\n");
}
void pmic_init(unsigned bus)
{
/*
* Don't need to set up VDD_CORE - already done - by OTP
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
*/
/* Restore PMIC POR defaults, in case kernel changed 'em */
pmic_slam_defaults(bus);
/* First set VDD_CPU to 1.2V, then enable the VDD_CPU regulator. */
pmic_write_reg(bus, 0x00, 0x50);
/* First set VDD_GPU to 1.0V, then enable the VDD_GPU regulator. */
pmic_write_reg(bus, 0x06, 0x28);
/* First set VPP_FUSE to 1.2V, then enable the VPP_FUSE regulator. */
pmic_write_reg(bus, 0x12, 0x10);
/*
* Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus.
* First set it to bypass 3.3V straight thru, then enable the regulator
*
* NOTE: We do this early because doing it later seems to hose the CPU
* power rail/partition startup. Need to debug.
*/
pmic_write_reg(bus, 0x16, 0x3f);
/*
* Panel power GPIO O4. Set mode for GPIO4 (0x0c to 7), then set
* the value (register 0x20 bit 4)
*/
pmic_write_reg(bus, 0x0c, 0x07);
pmic_write_reg(bus, 0x20, 0x10);
}
