int main(void)
{
power_on_delay();
timer0_init();
rfm70_init(RFM70_MODE_PTX, addr);
RED_LED_OUT();
RED_LED_OFF();
sei(); // enable interrupts globally
while(1)
{
sub_program_1hz();
}
}
//=====================================
void mcu_init(void)
//=====================================
{
CLK_Init();// base clock
power_on_delay(); //Power on delay
GPIO_Init();
TIM_Init();
//reset LoRa
PD_ODR=0b00000000;
delay_ms(20);
PD_ODR=0b00000100;
delay_ms(20);
FLASH_DeInit();
FLASH_Unlock(FLASH_MEMTYPE_DATA);
}
int main(void)
{
power_on_delay();
timer0_init();
RED_LED_OUT();
RED_LED_OFF();
if(rfm70_init(RFM70_MODE_PRX, addr) != 0) {
RED_LED_ON();
}
sei(); // enable interrupts globally
rfm70_set_ack_payload(RFM70_PIPE0, ack_pld, sizeof(ack_pld));
while(1)
{
Receive_Packet();
}
}
int main(void)
{
uint8_t i;
power_on_delay();
rfm70_init(RFM70_MODE_PRX, addr);
RED_LED_OUT();
RED_LED_OFF();
usbInit();
usbDeviceDisconnect(); /* Disconnect for some time to enforce reenumeration */
i = 0;
while(--i) {
_delay_ms(1);
}
usbDeviceConnect();
sei(); // enable interrupts globally
while(1)
{
usbPoll();
Receive_Packet();
}
}
int main(void) {
static struct apa_port_type port_0, port_1, port_2;
//
// set clock divider to /1
//
CLKPR = (1 << CLKPCE);
CLKPR = (0 << CLKPS3) | (0 << CLKPS2) | (0 << CLKPS1) | (0 << CLKPS0);
//
// initialize ADC
//
ADCSRB &= ~(1<<ADLAR); // right-adjust result
ADCSRA |= (1<<ADEN); // enable ADC
ADCSRA |= (1<<ADPS2); // set ADC prescalers to /128
ADCSRA |= (1<<ADPS1); // "
ADCSRA |= (1<<ADPS0); // "
//
// initialize PWM counter and pin
//
TCCR1A = ((1 << COM1B1) | (1 << COM1B0) | (1 << WGM11)
| (1 << WGM10)); // clear OC1B on compare match, fast 8-bit PWM
TCCR1B = ((0 << WGM13) | (1 << WGM12) | (0 << CS12) | (0 << CS11)
| (1 << CS10)); // /1 clock divider
OCR1B = 1023;
clear(PWM_port, PWM_pin);
output(PWM_direction, PWM_pin);
//
// initialize ports and pins
//
port_0.pins_in = &PINA;
port_0.port_out = &PORTB;
port_0.direction_out = &DDRB;
port_0.pin_in = (1 << PA7);
port_0.pin_out = (1 << PB2);
port_0.path_in_length = 0;
port_0.path_out_length = 0;
port_0.id = '0';
port_0.next_port = &port_1;
clear(*port_0.port_out, port_0.pin_out);
output(*port_0.direction_out, port_0.pin_out);
//
port_1.pins_in = &PINA;
port_1.port_out = &PORTA;
port_1.direction_out = &DDRA;
port_1.pin_in = (1 << PA0);
port_1.pin_out = (1 << PA1);
port_1.path_in_length = 0;
port_1.path_out_length = 0;
port_1.id = '1';
port_1.next_port = &port_2;
clear(*port_1.port_out, port_1.pin_out);
output(*port_1.direction_out, port_1.pin_out);
//
port_2.pins_in = &PINA;
port_2.port_out = &PORTA;
port_2.direction_out = &DDRA;
port_2.pin_in = (1 << PA4);
port_2.pin_out = (1 << PA6);
port_2.path_in_length = 0;
port_2.path_out_length = 0;
port_2.id = '2';
port_2.next_port = &port_0;
clear(*port_2.port_out, port_2.pin_out);
output(*port_2.direction_out, port_2.pin_out);
//
// power on delay
//
power_on_delay();
//
// main loop
//
while (1) {
apa_port_scan(&port_0);
apa_port_scan(&port_1);
apa_port_scan(&port_2);
}
}
