void QtSettingsProvider::removeProfile(const std::string& profile) {
QString profileStart(QString(profile.c_str()) + ":");
for (auto&& key : settings_.allKeys()) {
if (key.startsWith(profileStart)) {
settings_.remove(key);
}
}
QStringList stringList = settings_.value("profileList").toStringList();
stringList.removeAll(profile.c_str());
settings_.setValue("profileList", stringList);
updatePermissions();
}
VICP_Status VICP_wait(VICP_ResourceType resource)
/* ARGSUSED */
{
#ifdef _DBG_VERBOSE
printf("VICP_wait called \n");
#endif
/*
* Set the task priority to low over here
*/
/*
* When interrupt mode is not enabled then this poll word
* would be pointing to a location on ARM968 DTCM. If interrupt
* mode is enabled then setting this flag has no meaning.
*/
(*poll_word) |= 0x01;
/*
* Waiting for ARM968 to finish. In interrupt mode this flag will be
* set by HDVICP_Done function called by interrupt handler on ARM926
* side.
*/
while(((*poll_word) & 0x02) == 0); // bit 1 for ARM968 to start
#ifdef _DBG_VERBOSE
printf("Control is back to ARM926\n");
#endif
/*---------------------------------------------------------*/
/* Configuring timer-0 to start counting for the end portion
* of process call */
/*---------------------------------------------------------*/
#ifdef ENABLE_PROFILE_AT_FRM_LVL_ON_926
profileInit(0);
profileStart(0);
#endif
(*poll_word) &= 0xFFFFFFFD ; // Set the wait bit to 0 again
return (VICP_OK);
}
int main(int argc, char** argv)
{
// Prolog
initParallel(&argc, &argv);
profileStart(totalTimer);
initSubsystems();
timestampBarrier("Starting Initialization\n");
yamlAppInfo(yamlFile);
yamlAppInfo(screenOut);
Command cmd = parseCommandLine(argc, argv);
printCmdYaml(yamlFile, &cmd);
printCmdYaml(screenOut, &cmd);
SimFlat* sim = initSimulation(cmd);
printSimulationDataYaml(yamlFile, sim);
printSimulationDataYaml(screenOut, sim);
Validate* validate = initValidate(sim); // atom counts, energy
timestampBarrier("Initialization Finished\n");
timestampBarrier("Starting simulation\n");
// This is the CoMD main loop
const int nSteps = sim->nSteps;
const int printRate = sim->printRate;
int iStep = 0;
profileStart(loopTimer);
for (; iStep<nSteps;)
{
startTimer(commReduceTimer);
sumAtoms(sim);
stopTimer(commReduceTimer);
printThings(sim, iStep, getElapsedTime(timestepTimer));
startTimer(timestepTimer);
timestep(sim, printRate, sim->dt);
stopTimer(timestepTimer);
iStep += printRate;
}
profileStop(loopTimer);
sumAtoms(sim);
printThings(sim, iStep, getElapsedTime(timestepTimer));
timestampBarrier("Ending simulation\n");
// Epilog
validateResult(validate, sim);
profileStop(totalTimer);
printPerformanceResults(sim->atoms->nGlobal);
printPerformanceResultsYaml(yamlFile);
destroySimulation(&sim);
comdFree(validate);
finalizeSubsystems();
timestampBarrier("CoMD Ending\n");
destroyParallel();
return 0;
}